a7d006b637
The new code is based on timestamps, rather than delays. This eliminates the need to update every timer in timer_process(), which cost a non-trivial amount of CPU time on low-end machines. This involved changes to every user of the timer code, so this change almost certainly introduces bugs.
565 lines
28 KiB
C
565 lines
28 KiB
C
#include "ibm.h"
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#include "ide.h"
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#include "ide_atapi.h"
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#include "scsi.h"
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#include "timer.h"
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#define IDE_TIME (100 * TIMER_USEC)
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#define ATAPI_STATE_IDLE 0
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#define ATAPI_STATE_COMMAND 1
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#define ATAPI_STATE_GOT_COMMAND 2
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#define ATAPI_STATE_NEXT_PHASE 3
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#define ATAPI_STATE_READ_STATUS 4
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#define ATAPI_STATE_READ_MESSAGE 5
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#define ATAPI_STATE_END_PHASE 6
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#define ATAPI_STATE_READ_DATA 7
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#define ATAPI_STATE_READ_DATA_WAIT 8
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#define ATAPI_STATE_WRITE_DATA 9
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#define ATAPI_STATE_WRITE_DATA_WAIT 10
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#define ATAPI_STATE_RETRY_READ_DMA 11
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#define ATAPI_STATE_RETRY_WRITE_DMA 12
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#define FEATURES_DMA 0x01
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#define FEATURES_OVERLAP 0x02
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ATAPI *atapi;
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void atapi_data_write(atapi_device_t *atapi_dev, uint16_t val)
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{
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switch (atapi_dev->state)
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{
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case ATAPI_STATE_COMMAND:
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atapi_dev->command[atapi_dev->command_pos++] = val & 0xff;
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atapi_dev->command[atapi_dev->command_pos++] = val >> 8;
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if (atapi_dev->command_pos >= 12)
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{
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atapi_dev->state = ATAPI_STATE_GOT_COMMAND;
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timer_set_delay_u64(&ide_timer[atapi_dev->board], 6 * IDE_TIME);
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}
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break;
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case ATAPI_STATE_WRITE_DATA_WAIT:
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atapi_dev->data[atapi_dev->data_write_pos++] = val & 0xff;
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atapi_dev->data[atapi_dev->data_write_pos++] = val >> 8;
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// pclog("Write ATAPI data %i %i %i\n", atapi_dev->data_write_pos, atapi_dev->data_read_pos, idecallback[atapi_dev->board]);
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if (atapi_dev->data_write_pos >= atapi_dev->data_read_pos)
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{
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atapi_dev->bus_state = 0;
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atapi_dev->state = ATAPI_STATE_WRITE_DATA;
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timer_set_delay_u64(&ide_timer[atapi_dev->board], 6 * IDE_TIME);
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}
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break;
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}
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}
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uint16_t atapi_data_read(atapi_device_t *atapi_dev)
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{
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uint16_t temp = 0xffff;
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switch (atapi_dev->state)
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{
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case ATAPI_STATE_READ_DATA_WAIT:
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if (atapi_dev->data_read_pos >= atapi_dev->data_write_pos)
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{
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// pclog("ATAPI_STATE_READ_DATA_WAIT - out of data!\n");
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break;
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}
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temp = atapi_dev->data[atapi_dev->data_read_pos++];
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if (atapi_dev->data_read_pos < atapi_dev->data_write_pos)
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temp |= (atapi_dev->data[atapi_dev->data_read_pos++] << 8);
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// pclog("Read data %04x\n", temp);
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if (atapi_dev->data_read_pos >= atapi_dev->data_write_pos)
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{
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atapi_dev->state = ATAPI_STATE_NEXT_PHASE;
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timer_set_delay_u64(&ide_timer[atapi_dev->board], 6*IDE_TIME);
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}
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break;
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}
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return temp;
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}
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static int wait_for_bus(scsi_bus_t *bus, int state, int req_needed)
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{
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int c;
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for (c = 0; c < 20; c++)
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{
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int bus_state = scsi_bus_read(bus);
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if ((bus_state & (BUS_IO | BUS_CD | BUS_MSG)) == state && (bus_state & BUS_BSY))
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{
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if (!req_needed || (bus_state & BUS_REQ))
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return 1;
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}
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}
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return 0;
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}
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void atapi_command_start(atapi_device_t *atapi, uint8_t features)
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{
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scsi_bus_t *bus = &atapi->bus;
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atapi->use_dma = features & 1;
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scsi_bus_update(bus, BUS_SEL | BUS_SETDATA(1 << 0));
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if (!(scsi_bus_read(bus) & BUS_BSY))
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fatal("STATE_SCSI_SELECT failed to select target\n");
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scsi_bus_update(bus, 0);
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if (!(scsi_bus_read(bus) & BUS_BSY))
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fatal("STATE_SCSI_SELECT failed to select target 2\n");
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/*Device should now be selected*/
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if (!wait_for_bus(bus, BUS_CD, 1))
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fatal("Device failed to request command\n");
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atapi->state = ATAPI_STATE_COMMAND;
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atapi->command_pos = 0;
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}
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uint8_t atapi_read_iir(atapi_device_t *atapi_dev)
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{
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uint8_t val = 0;
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int bus_status = atapi_dev->bus_state;//scsi_bus_read(&atapi_dev->bus);
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if (bus_status & BUS_CD)
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val |= 1;
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if (bus_status & BUS_IO)
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val |= 2;
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// pclog("Read IIR %02X %02x\n", val, bus_status);
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return val;
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}
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uint8_t atapi_read_drq(atapi_device_t *atapi_dev)
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{
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return atapi_dev->bus_state & BUS_REQ;
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}
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void atapi_set_transfer_granularity(atapi_device_t *atapi_dev, int size)
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{
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if (atapi_dev->max_transfer_len > size)
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atapi_dev->max_transfer_len -= (atapi_dev->max_transfer_len % size);
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}
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void atapi_process_packet(atapi_device_t *atapi_dev)
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{
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// pclog("atapi_process_packet: state=%i\n", atapi_dev->state);
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switch (atapi_dev->state)
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{
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case ATAPI_STATE_COMMAND:
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*atapi_dev->atastat = READY_STAT | (*atapi_dev->atastat & ERR_STAT);
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atapi_dev->max_transfer_len = (*atapi_dev->cylinder) & ~1;
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if (!atapi_dev->max_transfer_len)
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atapi_dev->max_transfer_len = 0xfffe;
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atapi_dev->bus_state = BUS_CD | BUS_REQ;
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break;
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case ATAPI_STATE_GOT_COMMAND:
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{
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int pos = 0;
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int bus_state;
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int c;
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for (c = 0; c < 20; c++)
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{
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bus_state = scsi_bus_read(&atapi_dev->bus);
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if (!(bus_state & BUS_BSY))
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fatal("SEND_COMMAND - dropped BSY\n");
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if ((bus_state & (BUS_IO | BUS_CD | BUS_MSG)) != BUS_CD)
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fatal("SEND_COMMAND - bus phase incorrect\n");
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if (bus_state & BUS_REQ)
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break;
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}
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if (c == 20)
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fatal("SEND_COMMAND timed out\n");
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while (1)
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{
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int bus_out;
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for (c = 0; c < 20; c++)
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{
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int bus_state = scsi_bus_read(&atapi_dev->bus);
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if (!(bus_state & BUS_BSY))
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fatal("SEND_COMMAND - dropped BSY\n");
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if ((bus_state & (BUS_IO | BUS_CD | BUS_MSG)) != BUS_CD)
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break;
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if (bus_state & BUS_REQ)
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break;
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}
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if (c == 20)
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{
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// pclog("SEND_COMMAND timed out %x\n", scsi_bus_read(&atapi_dev->bus));
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atapi_dev->state = ATAPI_STATE_NEXT_PHASE;
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timer_set_delay_u64(&ide_timer[atapi_dev->board], 6 * IDE_TIME);
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break;
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}
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bus_state = scsi_bus_read(&atapi_dev->bus);
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if ((bus_state & (BUS_IO | BUS_CD | BUS_MSG | BUS_REQ)) != (BUS_CD | BUS_REQ))
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{
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// pclog("SEND_COMMAND - bus state changed %x\n", bus_state);
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atapi_dev->state = ATAPI_STATE_NEXT_PHASE;
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timer_set_delay_u64(&ide_timer[atapi_dev->board], 6 * IDE_TIME);
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break;
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}
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if (pos >= atapi_dev->command_pos)
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bus_out = BUS_SETDATA(0); /*Pad out with zeroes*/
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else
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bus_out = BUS_SETDATA(atapi_dev->command[pos++]);
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scsi_bus_update(&atapi_dev->bus, bus_out | BUS_ACK);
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scsi_bus_update(&atapi_dev->bus, bus_out & ~BUS_ACK);
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if (!(bus_state & BUS_BSY))
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fatal("SEND_COMMAND - dropped BSY\n");
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// if (pos >= atapi_dev->command_pos)
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// fatal("Out of data!\n");
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}
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}
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break;
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case ATAPI_STATE_NEXT_PHASE:
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{
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int c;
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for (c = 0; c < 20; c++)
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{
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int bus_state = scsi_bus_read(&atapi_dev->bus);
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// if (!c)
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// pclog("NEXT_PHASE - %x\n", bus_state);
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if (!(bus_state & BUS_BSY))
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fatal("NEXT_PHASE - dropped BSY waiting\n");
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if (bus_state & BUS_REQ)
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{
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scsi_device_t *scsi_dev = atapi_dev->bus.devices[0];
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void *scsi_data = atapi_dev->bus.device_data[0];
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switch (bus_state & (BUS_IO | BUS_CD | BUS_MSG))
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{
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case 0:
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atapi_dev->data_read_pos = scsi_dev->get_bytes_required(scsi_data);
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atapi_dev->data_write_pos = 0;
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if (atapi_dev->use_dma)
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{
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if (ide_bus_master_write_data)
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{
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if (ide_bus_master_write_data(atapi_dev->board, atapi_dev->data, atapi_dev->data_read_pos))
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{
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atapi_dev->state = ATAPI_STATE_RETRY_WRITE_DMA;
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timer_set_delay_u64(&ide_timer[atapi_dev->board], 1*IDE_TIME);
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}
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else
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{
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atapi_dev->data_write_pos = atapi_dev->data_read_pos;
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atapi_dev->bus_state = 0;
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atapi_dev->state = ATAPI_STATE_WRITE_DATA;
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timer_set_delay_u64(&ide_timer[atapi_dev->board], 6 * IDE_TIME);
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}
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}
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else
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{
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atapi_dev->state = ATAPI_STATE_RETRY_WRITE_DMA;
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timer_set_delay_u64(&ide_timer[atapi_dev->board], 1*IDE_TIME);
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}
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}
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else
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{
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if (atapi_dev->data_read_pos > atapi_dev->max_transfer_len)
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atapi_dev->data_read_pos = atapi_dev->max_transfer_len;
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atapi_dev->state = ATAPI_STATE_WRITE_DATA_WAIT;
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*atapi_dev->cylinder = atapi_dev->data_read_pos;
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// pclog("WRITE_DATA: bytes=%i\n", *atapi_dev->cylinder);
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*atapi_dev->atastat = READY_STAT | DRQ_STAT | (*atapi_dev->atastat & ERR_STAT);
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atapi_dev->bus_state = BUS_REQ;
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ide_irq_raise(atapi_dev->ide);
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}
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break;
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case BUS_IO:
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atapi_dev->state = ATAPI_STATE_READ_DATA;
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atapi_dev->data_read_pos = atapi_dev->data_write_pos = 0;
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break;
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case (BUS_IO | BUS_CD):
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atapi_dev->state = ATAPI_STATE_READ_STATUS;
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break;
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case (BUS_CD | BUS_IO | BUS_MSG):
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atapi_dev->state = ATAPI_STATE_READ_MESSAGE;
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break;
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default:
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fatal("NEXT_PHASE - bus state changed %x\n", bus_state);
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}
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break;
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}
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}
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timer_set_delay_u64(&ide_timer[atapi_dev->board], 6 * IDE_TIME);
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}
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break;
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case ATAPI_STATE_READ_STATUS:
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{
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int c;
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for (c = 0; c < 20; c++)
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{
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int bus_state = scsi_bus_read(&atapi_dev->bus);
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if (!(bus_state & BUS_BSY))
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fatal("READ_STATUS - dropped BSY waiting\n");
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if ((bus_state & (BUS_IO | BUS_CD | BUS_MSG)) != (BUS_CD | BUS_IO))
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fatal("READ_STATUS - changed phase\n");
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if (bus_state & BUS_REQ)
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{
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// uint8_t status = BUS_GETDATA(bus_state);
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int bus_out = 0;
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// pclog("Read status %02x\n", status);
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scsi_bus_update(&atapi_dev->bus, bus_out | BUS_ACK);
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scsi_bus_update(&atapi_dev->bus, bus_out & ~BUS_ACK);
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atapi_dev->state = ATAPI_STATE_NEXT_PHASE;
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break;
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}
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}
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timer_set_delay_u64(&ide_timer[atapi_dev->board], 6 * IDE_TIME);
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}
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break;
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case ATAPI_STATE_READ_MESSAGE:
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{
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int c;
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for (c = 0; c < 20; c++)
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{
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int bus_state = scsi_bus_read(&atapi_dev->bus);
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if (!(bus_state & BUS_BSY))
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fatal("READ_MESSAGE - dropped BSY waiting\n");
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if ((bus_state & (BUS_IO | BUS_CD | BUS_MSG)) != (BUS_CD | BUS_IO | BUS_MSG))
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{
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// pclog("READ_MESSAGE - changed phase\n");
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atapi_dev->state = ATAPI_STATE_NEXT_PHASE;
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break;
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}
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if (bus_state & BUS_REQ)
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{
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uint8_t msg = BUS_GETDATA(bus_state);
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int bus_out = 0;
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// pclog("Read message %02x\n", msg);
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scsi_bus_update(&atapi_dev->bus, bus_out | BUS_ACK);
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scsi_bus_update(&atapi_dev->bus, bus_out & ~BUS_ACK);
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switch (msg)
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{
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case MSG_COMMAND_COMPLETE:
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atapi_dev->state = ATAPI_STATE_END_PHASE;
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break;
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default:
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fatal("READ_MESSAGE - unknown message %02x\n", msg);
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}
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break;
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}
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}
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timer_set_delay_u64(&ide_timer[atapi_dev->board], 6 * IDE_TIME);
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}
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break;
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case ATAPI_STATE_READ_DATA:
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{
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while (atapi_dev->data_write_pos < atapi_dev->max_transfer_len)
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{
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int c;
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for (c = 0; c < 20; c++)
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{
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int bus_state = scsi_bus_read(&atapi_dev->bus);
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if (!(bus_state & BUS_BSY))
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fatal("READ_DATA - dropped BSY waiting\n");
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if ((bus_state & (BUS_IO | BUS_CD | BUS_MSG)) != BUS_IO)
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{
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// pclog("READ_DATA - changed phase\n");
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break;
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}
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if (bus_state & BUS_REQ)
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{
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uint8_t data = BUS_GETDATA(bus_state);
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int bus_out = 0;
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atapi_dev->data[atapi_dev->data_write_pos++] = data;
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// pclog("Read data %02x %i\n", data, atapi_dev->data_write_pos);
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scsi_bus_update(&atapi_dev->bus, bus_out | BUS_ACK);
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scsi_bus_update(&atapi_dev->bus, bus_out & ~BUS_ACK);
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break;
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}
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}
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if ((scsi_bus_read(&atapi_dev->bus) & (BUS_IO | BUS_CD | BUS_MSG)) != BUS_IO)
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break;
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}
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if (atapi_dev->use_dma)
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{
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if (ide_bus_master_read_data)
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{
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if (ide_bus_master_read_data(atapi_dev->board, atapi_dev->data, atapi_dev->data_write_pos))
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{
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atapi_dev->state = ATAPI_STATE_RETRY_READ_DMA;
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timer_set_delay_u64(&ide_timer[atapi_dev->board], 1*IDE_TIME);
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}
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else
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{
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atapi_dev->state = ATAPI_STATE_NEXT_PHASE;
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timer_set_delay_u64(&ide_timer[atapi_dev->board], 1*IDE_TIME);
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}
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}
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else
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{
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atapi_dev->state = ATAPI_STATE_RETRY_READ_DMA;
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timer_set_delay_u64(&ide_timer[atapi_dev->board], 1*IDE_TIME);
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}
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}
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else
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{
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atapi_dev->state = ATAPI_STATE_READ_DATA_WAIT;
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*atapi_dev->atastat = READY_STAT | DRQ_STAT | (*atapi_dev->atastat & ERR_STAT);
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*atapi_dev->cylinder = atapi_dev->data_write_pos;
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// pclog("READ_DATA: bytes=%i\n", *atapi_dev->cylinder);
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atapi_dev->bus_state = BUS_IO | BUS_REQ;
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ide_irq_raise(atapi_dev->ide);
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}
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}
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break;
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case ATAPI_STATE_WRITE_DATA:
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{
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atapi_dev->data_read_pos = 0;
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// pclog("ATAPI_STATE_WRITE_DATA - %i\n", atapi_dev->data_write_pos);
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while (atapi_dev->data_read_pos < atapi_dev->data_write_pos)
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{
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int bus_state = scsi_bus_read(&atapi_dev->bus);
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if (!(bus_state & BUS_BSY))
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fatal("WRITE_DATA - dropped BSY waiting\n");
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if ((bus_state & (BUS_IO | BUS_CD | BUS_MSG)) != 0)
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{
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// pclog("WRITE_DATA - changed phase\n");
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atapi_dev->state = ATAPI_STATE_NEXT_PHASE;
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break;
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}
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if (bus_state & BUS_REQ)
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{
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uint8_t data = atapi_dev->data[atapi_dev->data_read_pos++];
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int bus_out;
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|
|
// pclog("Write data %02x %i\n", data, atapi_dev->data_read_pos-1);
|
|
bus_out = BUS_SETDATA(data);
|
|
scsi_bus_update(&atapi_dev->bus, bus_out | BUS_ACK);
|
|
scsi_bus_update(&atapi_dev->bus, bus_out & ~BUS_ACK);
|
|
}
|
|
}
|
|
|
|
atapi_dev->state = ATAPI_STATE_NEXT_PHASE;
|
|
timer_set_delay_u64(&ide_timer[atapi_dev->board], 1 * IDE_TIME);
|
|
}
|
|
break;
|
|
|
|
case ATAPI_STATE_END_PHASE:
|
|
{
|
|
int c;
|
|
/*Wait for SCSI command to move to next phase*/
|
|
for (c = 0; c < 20; c++)
|
|
{
|
|
int bus_state = scsi_bus_read(&atapi_dev->bus);
|
|
|
|
if (!(bus_state & BUS_BSY))
|
|
{
|
|
// pclog("END_PHASE - dropped BSY waiting\n");
|
|
atapi_dev->state = ATAPI_STATE_IDLE;
|
|
break;
|
|
}
|
|
|
|
if (bus_state & BUS_REQ)
|
|
fatal("END_PHASE - unexpected REQ\n");
|
|
}
|
|
if (atapi_dev->state == ATAPI_STATE_IDLE)
|
|
{
|
|
scsi_device_t *scsi_dev = atapi_dev->bus.devices[0];
|
|
void *scsi_data = atapi_dev->bus.device_data[0];
|
|
|
|
*atapi_dev->atastat = READY_STAT;
|
|
atapi_dev->bus_state = BUS_IO | BUS_CD;
|
|
if (scsi_dev->get_status(scsi_data) != STATUS_GOOD)
|
|
{
|
|
*atapi_dev->error = (scsi_dev->get_sense_key(scsi_data) << 4) | ABRT_ERR;
|
|
if (scsi_dev->get_sense_key(scsi_data) == KEY_UNIT_ATTENTION)
|
|
*atapi_dev->error |= MCR_ERR;
|
|
*atapi_dev->atastat |= ERR_STAT;
|
|
}
|
|
ide_irq_raise(atapi_dev->ide);
|
|
}
|
|
else
|
|
timer_set_delay_u64(&ide_timer[atapi_dev->board], 6 * IDE_TIME);
|
|
}
|
|
break;
|
|
|
|
case ATAPI_STATE_RETRY_READ_DMA:
|
|
{
|
|
if (ide_bus_master_read_data(atapi_dev->board, atapi_dev->data, atapi_dev->data_write_pos))
|
|
{
|
|
timer_set_delay_u64(&ide_timer[atapi_dev->board], 1*IDE_TIME);
|
|
}
|
|
else
|
|
{
|
|
atapi_dev->state = ATAPI_STATE_NEXT_PHASE;
|
|
timer_set_delay_u64(&ide_timer[atapi_dev->board], 6*IDE_TIME);
|
|
}
|
|
}
|
|
break;
|
|
|
|
case ATAPI_STATE_RETRY_WRITE_DMA:
|
|
{
|
|
if (ide_bus_master_write_data(atapi_dev->board, atapi_dev->data, atapi_dev->data_read_pos))
|
|
{
|
|
timer_set_delay_u64(&ide_timer[atapi_dev->board], 1*IDE_TIME);
|
|
}
|
|
else
|
|
{
|
|
atapi_dev->bus_state = 0;
|
|
atapi_dev->state = ATAPI_STATE_WRITE_DATA;
|
|
timer_set_delay_u64(&ide_timer[atapi_dev->board], 6 * IDE_TIME);
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
}
|