96 lines
3.8 KiB
C
96 lines
3.8 KiB
C
#include <string.h>
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#include "ibm.h"
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#include "io.h"
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#include "mem.h"
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#include "pci.h"
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#include "i430vx.h"
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static uint8_t card_i430vx[256];
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static void i430vx_map(uint32_t addr, uint32_t size, int state)
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{
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switch (state & 3)
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{
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case 0x0: mem_bios_set_state(addr, size, 0, 0); break; /*DRAM disabled, accesses directed to PCI bus*/
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case 0x1: mem_bios_set_state(addr, size, 1, 0); break; /*Read only, DRAM write protected, non-cacheable*/
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case 0x2: mem_bios_set_state(addr, size, 0, 1); break; /*Write only*/
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case 0x3: mem_bios_set_state(addr, size, 1, 1); break; /*Read/write, non-cacheable*/
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/*Below are redundant*/
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// case 0x5: mem_sethandler(addr, size, mem_read_ram, mem_read_ramw, mem_read_raml, NULL, NULL, NULL ); break; /*Read only, DRAM write protected, cacheable*/
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// case 0x7: mem_sethandler(addr, size, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml); break; /*Read/write, non-cacheable*/
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}
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flushmmucache_nopc();
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}
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void i430vx_write(int func, int addr, uint8_t val, void *priv)
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{
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if (func)
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return;
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switch (addr)
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{
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case 0x00: case 0x01: case 0x02: case 0x03:
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case 0x08: case 0x09: case 0x0a: case 0x0b:
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case 0x0e:
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return;
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case 0x59: /*PAM0*/
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if ((card_i430vx[0x59] ^ val) & 0xf0)
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{
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i430vx_map(0xf0000, 0x10000, val >> 4);
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shadowbios = (val & 0x10);
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}
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pclog("i430vx_write : PAM0 write %02X\n", val);
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break;
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case 0x5e: /*PAM5*/
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if ((card_i430vx[0x5e] ^ val) & 0x0f)
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i430vx_map(0xe0000, 0x04000, val & 0xf);
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if ((card_i430vx[0x5e] ^ val) & 0xf0)
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i430vx_map(0xe4000, 0x04000, val >> 4);
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pclog("i430vx_write : PAM5 write %02X\n", val);
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break;
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case 0x5f: /*PAM6*/
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if ((card_i430vx[0x5f] ^ val) & 0x0f)
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i430vx_map(0xe8000, 0x04000, val & 0xf);
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if ((card_i430vx[0x5f] ^ val) & 0xf0)
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i430vx_map(0xec000, 0x04000, val >> 4);
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pclog("i430vx_write : PAM6 write %02X\n", val);
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break;
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}
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card_i430vx[addr] = val;
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}
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uint8_t i430vx_read(int func, int addr, void *priv)
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{
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if (func)
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return 0xff;
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return card_i430vx[addr];
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}
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void i430vx_init()
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{
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pci_add_specific(0, i430vx_read, i430vx_write, NULL);
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memset(card_i430vx, 0, 256);
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card_i430vx[0x00] = 0x86; card_i430vx[0x01] = 0x80; /*Intel*/
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card_i430vx[0x02] = 0x30; card_i430vx[0x03] = 0x70; /*82437VX*/
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card_i430vx[0x04] = 0x06; card_i430vx[0x05] = 0x00;
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card_i430vx[0x06] = 0x00; card_i430vx[0x07] = 0x02;
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card_i430vx[0x08] = 0x00; /*A0 stepping*/
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card_i430vx[0x09] = 0x00; card_i430vx[0x0a] = 0x00; card_i430vx[0x0b] = 0x06;
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card_i430vx[0x52] = 0x42; /*256kb PLB cache*/
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card_i430vx[0x53] = 0x14;
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card_i430vx[0x56] = 0x52; /*DRAM control*/
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card_i430vx[0x57] = 0x01;
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card_i430vx[0x60] = card_i430vx[0x61] = card_i430vx[0x62] = card_i430vx[0x63] = card_i430vx[0x64] = 0x02;
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card_i430vx[0x67] = 0x11;
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card_i430vx[0x69] = 0x03;
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card_i430vx[0x70] = 0x20;
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card_i430vx[0x72] = 0x02;
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card_i430vx[0x74] = 0x0e;
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card_i430vx[0x78] = 0x23;
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}
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