1033 lines
36 KiB
C
1033 lines
36 KiB
C
/*Trident TVGA (8900D) emulation*/
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#include <stdlib.h>
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#include "ibm.h"
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#include "device.h"
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#include "io.h"
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#include "mem.h"
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#include "video.h"
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#include "vid_svga.h"
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#include "vid_svga_render.h"
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#include "vid_tkd8001_ramdac.h"
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#include "vid_tvga.h"
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typedef struct tvga_t
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{
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mem_mapping_t linear_mapping;
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mem_mapping_t accel_mapping;
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svga_t svga;
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tkd8001_ramdac_t ramdac;
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struct
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{
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uint16_t src_x, src_y;
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uint16_t dst_x, dst_y;
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uint16_t size_x, size_y;
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uint16_t fg_col, bg_col;
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uint8_t rop;
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uint16_t flags;
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uint8_t pattern[0x80];
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int command;
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int offset;
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uint8_t ger22;
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int x, y;
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uint32_t src, dst, src_old, dst_old;
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int pat_x, pat_y;
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int use_src;
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int pitch, bpp;
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uint16_t tvga_pattern[8][8];
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} accel;
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uint8_t tvga_3d8, tvga_3d9;
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int oldmode;
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uint8_t oldctrl2,newctrl2;
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uint32_t linear_base, linear_size;
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} tvga_t;
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void tvga_recalcmapping(tvga_t *tvga);
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uint8_t tvga_accel_read(uint32_t addr, void *priv);
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uint16_t tvga_accel_read_w(uint32_t addr, void *priv);
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uint32_t tvga_accel_read_l(uint32_t addr, void *priv);
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void tvga_accel_write(uint32_t addr, uint8_t val, void *priv);
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void tvga_accel_write_w(uint32_t addr, uint16_t val, void *priv);
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void tvga_accel_write_l(uint32_t addr, uint32_t val, void *priv);
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void tvga_accel_write_fb_l(uint32_t addr, uint32_t val, void *priv);
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void tvga_out(uint16_t addr, uint8_t val, void *p)
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{
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tvga_t *tvga = (tvga_t *)p;
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svga_t *svga = &tvga->svga;
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uint8_t old;
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// pclog("tvga_out : %04X %02X %04X:%04X %i\n", addr, val, CS,pc, bpp);
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if (((addr&0xFFF0) == 0x3D0 || (addr&0xFFF0) == 0x3B0) && !(svga->miscout & 1)) addr ^= 0x60;
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switch (addr)
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{
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case 0x3C5:
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switch (svga->seqaddr & 0xf)
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{
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case 0xB:
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tvga->oldmode=1;
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break;
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case 0xC:
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if (svga->seqregs[0xe] & 0x80)
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svga->seqregs[0xc] = val;
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break;
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case 0xd:
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if (tvga->oldmode)
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tvga->oldctrl2 = val;
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else
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tvga->newctrl2=val;
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break;
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case 0xE:
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svga->seqregs[0xe] = val ^ 2;
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svga->write_bank = (svga->seqregs[0xe] & 0xf) * 65536;
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if (!(svga->gdcreg[0xf] & 1))
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svga->read_bank = svga->write_bank;
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return;
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}
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break;
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case 0x3C6: case 0x3C7: case 0x3C8: case 0x3C9:
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if (gfxcard != GFX_TGUI9440)
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{
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tkd8001_ramdac_out(addr, val, &tvga->ramdac, svga);
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return;
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}
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break;
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case 0x3CF:
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switch (svga->gdcaddr & 15)
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{
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case 0x6:
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if (svga->gdcreg[6] != val)
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{
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svga->gdcreg[6] = val;
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tvga_recalcmapping(tvga);
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}
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return;
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case 0xE:
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svga->gdcreg[0xe] = val ^ 2;
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if ((svga->gdcreg[0xf] & 1) == 1)
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svga->read_bank = (svga->gdcreg[0xe] & 0xf) * 65536;
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break;
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case 0xF:
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if (val & 1) svga->read_bank = (svga->gdcreg[0xe] & 0xf) *65536;
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else svga->read_bank = (svga->seqregs[0xe] & 0xf) *65536;
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svga->write_bank = (svga->seqregs[0xe] & 0xf) * 65536;
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break;
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}
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break;
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case 0x3D4:
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if (gfxcard == GFX_TGUI9440) svga->crtcreg = val & 0x7f;
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else svga->crtcreg = val & 0x3f;
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return;
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case 0x3D5:
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if (svga->crtcreg <= 7 && svga->crtc[0x11] & 0x80) return;
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old = svga->crtc[svga->crtcreg];
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svga->crtc[svga->crtcreg] = val;
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//if (crtcreg!=0xE && crtcreg!=0xF) pclog("CRTC R%02X = %02X\n",crtcreg,val);
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if (old != val)
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{
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if (svga->crtcreg < 0xE || svga->crtcreg > 0x10)
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{
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svga->fullchange = changeframecount;
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svga_recalctimings(svga);
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}
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}
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switch (svga->crtcreg)
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{
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case 0x21:
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if (old != val)
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tvga_recalcmapping(tvga);
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break;
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case 0x38: /*Pixel bus register*/
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// pclog("Pixel bus register %02X\n", val);
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if (gfxcard != GFX_TGUI9440)
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break;
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if ((val & 0xc) == 4) svga->bpp = 16;
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else if (!(val & 0xc)) svga->bpp = 8;
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else svga->bpp = 24;
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break;
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case 0x40: case 0x41: case 0x42: case 0x43:
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case 0x44: case 0x45: case 0x46: case 0x47:
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svga->hwcursor.x = (svga->crtc[0x40] | (svga->crtc[0x41] << 8)) & 0x7ff;
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svga->hwcursor.y = (svga->crtc[0x42] | (svga->crtc[0x43] << 8)) & 0x7ff;
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svga->hwcursor.xoff = svga->crtc[0x46] & 0x3f;
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svga->hwcursor.yoff = svga->crtc[0x47] & 0x3f;
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svga->hwcursor.addr = (svga->crtc[0x44] << 10) | ((svga->crtc[0x45] & 0x7) << 18) | (svga->hwcursor.yoff * 8);
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break;
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case 0x50:
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svga->hwcursor.ena = val & 0x80;
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break;
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}
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return;
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case 0x3D8:
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tvga->tvga_3d8 = val;
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if (svga->gdcreg[0xf] & 4)
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{
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svga->write_bank = (val & 0x1f) * 65536;
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// pclog("SVGAWBANK 3D8 %08X %04X:%04X\n",svgawbank,CS,pc);
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if (!(svga->gdcreg[0xf] & 1))
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{
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svga->read_bank = (val & 0x1f) * 65536;
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// pclog("SVGARBANK 3D8 %08X %04X:%04X\n",svgarbank,CS,pc);
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}
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}
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return;
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case 0x3D9:
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tvga->tvga_3d9=val;
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if ((svga->gdcreg[0xf] & 5) == 5)
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{
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svga->read_bank = (val & 0x1F) * 65536;
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// pclog("SVGARBANK 3D9 %08X %04X:%04X\n",svgarbank,CS,pc);
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}
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return;
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}
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svga_out(addr, val, svga);
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}
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uint8_t tvga_in(uint16_t addr, void *p)
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{
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tvga_t *tvga = (tvga_t *)p;
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svga_t *svga = &tvga->svga;
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// if (addr != 0x3da) pclog("tvga_in : %04X %04X:%04X\n", addr, CS,pc);
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if (((addr&0xFFF0) == 0x3D0 || (addr&0xFFF0) == 0x3B0) && !(svga->miscout & 1)) addr ^= 0x60;
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switch (addr)
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{
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case 0x3C5:
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if ((svga->seqaddr & 0xf) == 0xb)
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{
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// printf("Read Trident ID %04X:%04X %04X\n",CS,pc,readmemw(ss,SP));
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tvga->oldmode = 0;
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if (gfxcard == GFX_TVGA) return 0x33; /*TVGA8900D*/
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else return 0xe3; /*TGUI9440AGi*/
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}
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if ((svga->seqaddr & 0xf) == 0xc)
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{
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// printf("Read Trident Power Up 1 %04X:%04X %04X\n",CS,pc,readmemw(ss,SP));
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// return 0x20; /*2 DRAM banks*/
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}
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if ((svga->seqaddr & 0xf) == 0xd)
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{
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if (tvga->oldmode) return tvga->oldctrl2;
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return tvga->newctrl2;
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}
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break;
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case 0x3C6: case 0x3C7: case 0x3C8: case 0x3C9:
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if (gfxcard != GFX_TGUI9440)
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return tkd8001_ramdac_in(addr, &tvga->ramdac, svga);
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break;
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case 0x3D4:
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return svga->crtcreg;
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case 0x3D5:
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return svga->crtc[svga->crtcreg];
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case 0x3d8:
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return tvga->tvga_3d8;
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case 0x3d9:
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return tvga->tvga_3d9;
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}
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return svga_in(addr, svga);
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}
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void tvga_recalctimings(svga_t *svga)
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{
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tvga_t *tvga = (tvga_t *)svga->p;
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if (!svga->rowoffset) svga->rowoffset = 0x100; /*This is the only sensible way I can see this being handled,
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given that TVGA8900D has no overflow bits.
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Some sort of overflow is required for 320x200x24 and 1024x768x16*/
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if ((svga->crtc[0x1e] & 0xA0) == 0xA0) svga->ma_latch |= 0x10000;
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if ((svga->crtc[0x27] & 0x01) == 0x01) svga->ma_latch |= 0x20000;
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if ((svga->crtc[0x27] & 0x02) == 0x02) svga->ma_latch |= 0x40000;
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if (tvga->oldctrl2 & 0x10)
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{
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svga->rowoffset <<= 1;
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svga->ma_latch <<= 1;
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}
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if (tvga->oldctrl2 & 0x10) /*I'm not convinced this is the right register for this function*/
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svga->lowres=0;
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if (gfxcard == GFX_TGUI9440)
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svga->lowres = !(svga->crtc[0x2a] & 0x40);
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if (svga->gdcreg[0xf] & 8)
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{
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svga->htotal <<= 1;
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svga->hdisp <<= 1;
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}
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svga->interlace = svga->crtc[0x1e] & 4;
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if (svga->interlace)
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svga->rowoffset >>= 1;
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switch (((svga->miscout >> 2) & 3) | ((tvga->newctrl2 << 2) & 4))
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{
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case 2: svga->clock = cpuclock/44900000.0; break;
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case 3: svga->clock = cpuclock/36000000.0; break;
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case 4: svga->clock = cpuclock/57272000.0; break;
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case 5: svga->clock = cpuclock/65000000.0; break;
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case 6: svga->clock = cpuclock/50350000.0; break;
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case 7: svga->clock = cpuclock/40000000.0; break;
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}
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if ((tvga->oldctrl2 & 0x10) || (gfxcard == GFX_TGUI9440 && (svga->crtc[0x2a] & 0x40)))
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{
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switch (svga->bpp)
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{
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case 8:
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svga->render = svga_render_8bpp_highres;
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break;
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case 15:
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svga->render = svga_render_15bpp_highres;
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break;
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case 16:
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svga->render = svga_render_16bpp_highres;
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break;
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case 24:
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svga->render = svga_render_24bpp_highres;
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break;
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case 32:
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svga->render = svga_render_32bpp_highres;
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break;
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}
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}
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}
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void tvga_recalcmapping(tvga_t *tvga)
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{
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svga_t *svga = &tvga->svga;
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// pclog("tvga_recalcmapping : %02X %02X\n", svga->crtc[0x21], svga->gdcreg[6]);
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if (svga->crtc[0x21] & 0x20)
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{
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mem_mapping_disable(&svga->mapping);
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tvga->linear_base = ((svga->crtc[0x21] & 0xf) | ((svga->crtc[0x21] >> 2) & 0x30)) << 20;
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tvga->linear_size = (svga->crtc[0x21] & 0x10) ? 0x200000 : 0x100000;
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mem_mapping_set_addr(&tvga->linear_mapping, tvga->linear_base, tvga->linear_size);
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// pclog("Trident linear framebuffer at %08X - size %06X\n", tvga->linear_base, tvga->linear_size);
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mem_mapping_enable(&tvga->accel_mapping);
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}
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else
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{
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// pclog("Write mapping %02X\n", val);
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mem_mapping_disable(&tvga->linear_mapping);
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mem_mapping_disable(&tvga->accel_mapping);
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switch (svga->gdcreg[6] & 0xC)
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{
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case 0x0: /*128k at A0000*/
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mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000);
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break;
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case 0x4: /*64k at A0000*/
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mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000);
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mem_mapping_enable(&tvga->accel_mapping);
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break;
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case 0x8: /*32k at B0000*/
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mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000);
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break;
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case 0xC: /*32k at B8000*/
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mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000);
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break;
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}
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}
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}
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void tvga_hwcursor_draw(svga_t *svga, int displine)
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{
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uint32_t dat[2];
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int xx;
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int offset = svga->hwcursor_latch.x - svga->hwcursor_latch.xoff;
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dat[0] = (svga->vram[svga->hwcursor_latch.addr] << 24) | (svga->vram[svga->hwcursor_latch.addr + 1] << 16) | (svga->vram[svga->hwcursor_latch.addr + 2] << 8) | svga->vram[svga->hwcursor_latch.addr + 3];
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dat[1] = (svga->vram[svga->hwcursor_latch.addr + 4] << 24) | (svga->vram[svga->hwcursor_latch.addr + 5] << 16) | (svga->vram[svga->hwcursor_latch.addr + 6] << 8) | svga->vram[svga->hwcursor_latch.addr + 7];
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for (xx = 0; xx < 32; xx++)
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{
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if (offset >= svga->hwcursor_latch.x)
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{
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if (!(dat[0] & 0x80000000))
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((uint32_t *)buffer32->line[displine])[offset + 32] = (dat[1] & 0x80000000) ? 0xffffff : 0;
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else if (dat[1] & 0x80000000)
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((uint32_t *)buffer32->line[displine])[offset + 32] ^= 0xffffff;
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// pclog("Plot %i, %i (%i %i) %04X %04X\n", offset, displine, x+xx, svga_hwcursor_on, dat[0], dat[1]);
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}
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offset++;
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dat[0] <<= 1;
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dat[1] <<= 1;
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}
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svga->hwcursor_latch.addr += 8;
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}
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void *tvga8900d_init()
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{
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tvga_t *tvga = malloc(sizeof(tvga_t));
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memset(tvga, 0, sizeof(tvga_t));
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svga_init(&tvga->svga, tvga, 1 << 20, /*1mb - chip supports 2mb, but drivers are buggy*/
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tvga_recalctimings,
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tvga_in, tvga_out,
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NULL);
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mem_mapping_add(&tvga->linear_mapping, 0, 0, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, &tvga->svga);
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mem_mapping_add(&tvga->accel_mapping, 0xbc000, 0x4000, tvga_accel_read, tvga_accel_read_w, tvga_accel_read_l, tvga_accel_write, tvga_accel_write_w, tvga_accel_write_l, tvga);
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mem_mapping_disable(&tvga->linear_mapping);
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mem_mapping_disable(&tvga->accel_mapping);
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io_sethandler(0x03c0, 0x0020, tvga_in, NULL, NULL, tvga_out, NULL, NULL, tvga);
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return tvga;
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}
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void *tgui9440_init()
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{
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tvga_t *tvga = malloc(sizeof(tvga_t));
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memset(tvga, 0, sizeof(tvga_t));
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svga_init(&tvga->svga, tvga, 1 << 21, /*2mb*/
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tvga_recalctimings,
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tvga_in, tvga_out,
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tvga_hwcursor_draw);
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mem_mapping_add(&tvga->linear_mapping, 0, 0, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, &tvga->svga);
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mem_mapping_add(&tvga->accel_mapping, 0xbc000, 0x4000, tvga_accel_read, tvga_accel_read_w, tvga_accel_read_l, tvga_accel_write, tvga_accel_write_w, tvga_accel_write_l, tvga);
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mem_mapping_disable(&tvga->accel_mapping);
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io_sethandler(0x03c0, 0x0020, tvga_in, NULL, NULL, tvga_out, NULL, NULL, tvga);
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return tvga;
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}
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void tvga_close(void *p)
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{
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tvga_t *tvga = (tvga_t *)p;
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svga_close(&tvga->svga);
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free(tvga);
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}
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void tvga_speed_changed(void *p)
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{
|
|
tvga_t *tvga = (tvga_t *)p;
|
|
|
|
svga_recalctimings(&tvga->svga);
|
|
}
|
|
|
|
void tvga_force_redraw(void *p)
|
|
{
|
|
tvga_t *tvga = (tvga_t *)p;
|
|
|
|
tvga->svga.fullchange = changeframecount;
|
|
}
|
|
|
|
device_t tvga8900d_device =
|
|
{
|
|
"Trident TVGA 8900D",
|
|
tvga8900d_init,
|
|
tvga_close,
|
|
tvga_speed_changed,
|
|
tvga_force_redraw,
|
|
svga_add_status_info
|
|
};
|
|
device_t tgui9440_device =
|
|
{
|
|
"Trident TGUI 9440",
|
|
tgui9440_init,
|
|
tvga_close,
|
|
tvga_speed_changed,
|
|
tvga_force_redraw,
|
|
svga_add_status_info
|
|
};
|
|
|
|
enum
|
|
{
|
|
TGUI_BITBLT = 1
|
|
};
|
|
|
|
enum
|
|
{
|
|
TGUI_SRCCPU = 0,
|
|
|
|
TGUI_SRCDISP = 0x04, /*Source is from display*/
|
|
TGUI_PATMONO = 0x20, /*Pattern is monochrome and needs expansion*/
|
|
TGUI_SRCMONO = 0x40, /*Source is monochrome from CPU and needs expansion*/
|
|
TGUI_TRANSENA = 0x1000, /*Transparent (no draw when source == bg col)*/
|
|
TGUI_TRANSREV = 0x2000, /*Reverse fg/bg for transparent*/
|
|
TGUI_SOLIDFILL = 0x4000 /*Pattern all zero?*/
|
|
};
|
|
|
|
#define READ(addr, dat) if (tvga->accel.bpp == 0) dat = svga->vram[addr & 0x1fffff]; \
|
|
else dat = vram_w[addr & 0xfffff];
|
|
|
|
#define MIX() do \
|
|
{ \
|
|
out = 0; \
|
|
for (c=0;c<16;c++) \
|
|
{ \
|
|
d=(dst_dat & (1<<c)) ? 1:0; \
|
|
if (src_dat & (1<<c)) d|=2; \
|
|
if (pat_dat & (1<<c)) d|=4; \
|
|
if (tvga->accel.rop & (1<<d)) out|=(1<<c); \
|
|
} \
|
|
} while (0)
|
|
|
|
#define WRITE(addr, dat) if (tvga->accel.bpp == 0) \
|
|
{ \
|
|
svga->vram[addr & 0x1fffff] = dat; \
|
|
svga->changedvram[((addr) & 0x1fffff) >> 10] = changeframecount; \
|
|
} \
|
|
else \
|
|
{ \
|
|
vram_w[addr & 0xfffff] = dat; \
|
|
svga->changedvram[((addr) & 0xfffff) >> 9] = changeframecount; \
|
|
}
|
|
|
|
void tvga_accel_write_fb_b(uint32_t addr, uint8_t val, void *priv);
|
|
void tvga_accel_write_fb_w(uint32_t addr, uint16_t val, void *priv);
|
|
|
|
void tvga_accel_command(int count, uint32_t cpu_dat, tvga_t *tvga)
|
|
{
|
|
svga_t *svga = &tvga->svga;
|
|
int x, y;
|
|
int c, d;
|
|
uint16_t src_dat, dst_dat, pat_dat;
|
|
uint16_t out;
|
|
int xdir = (tvga->accel.flags & 0x200) ? -1 : 1;
|
|
int ydir = (tvga->accel.flags & 0x100) ? -1 : 1;
|
|
uint16_t trans_col = (tvga->accel.flags & TGUI_TRANSREV) ? tvga->accel.fg_col : tvga->accel.bg_col;
|
|
uint16_t *vram_w = (uint16_t *)svga->vram;
|
|
|
|
if (tvga->accel.bpp == 0)
|
|
trans_col &= 0xff;
|
|
|
|
if (count != -1 && !tvga->accel.x)
|
|
{
|
|
count -= tvga->accel.offset;
|
|
cpu_dat <<= tvga->accel.offset;
|
|
}
|
|
if (count == -1)
|
|
{
|
|
tvga->accel.x = tvga->accel.y = 0;
|
|
}
|
|
if (tvga->accel.flags & TGUI_SOLIDFILL)
|
|
{
|
|
// pclog("SOLIDFILL\n");
|
|
for (y = 0; y < 8; y++)
|
|
{
|
|
for (x = 0; x < 8; x++)
|
|
{
|
|
tvga->accel.tvga_pattern[y][x] = tvga->accel.fg_col;
|
|
}
|
|
}
|
|
}
|
|
else if (tvga->accel.flags & TGUI_PATMONO)
|
|
{
|
|
// pclog("PATMONO\n");
|
|
for (y = 0; y < 8; y++)
|
|
{
|
|
for (x = 0; x < 8; x++)
|
|
{
|
|
tvga->accel.tvga_pattern[y][x] = (tvga->accel.pattern[y] & (1 << x)) ? tvga->accel.fg_col : tvga->accel.bg_col;
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
// pclog("OTHER\n");
|
|
for (y = 0; y < 8; y++)
|
|
{
|
|
for (x = 0; x < 8; x++)
|
|
{
|
|
tvga->accel.tvga_pattern[y][x] = tvga->accel.pattern[x + y*8];
|
|
}
|
|
}
|
|
}
|
|
/* for (y = 0; y < 8; y++)
|
|
{
|
|
if (count == -1) pclog("Pattern %i : %02X %02X %02X %02X %02X %02X %02X %02X\n", y, tvga->accel.tvga_pattern[y][0], tvga->accel.tvga_pattern[y][1], tvga->accel.tvga_pattern[y][2], tvga->accel.tvga_pattern[y][3], tvga->accel.tvga_pattern[y][4], tvga->accel.tvga_pattern[y][5], tvga->accel.tvga_pattern[y][6], tvga->accel.tvga_pattern[y][7]);
|
|
}*/
|
|
// if (count == -1) pclog("Command %i %i %p\n", tvga->accel.command, TGUI_BITBLT, tvga);
|
|
switch (tvga->accel.command)
|
|
{
|
|
case TGUI_BITBLT:
|
|
// if (count == -1) pclog("BITBLT src %i,%i dst %i,%i size %i,%i flags %04X\n", tvga->accel.src_x, tvga->accel.src_y, tvga->accel.dst_x, tvga->accel.dst_y, tvga->accel.size_x, tvga->accel.size_y, tvga->accel.flags);
|
|
if (count == -1)
|
|
{
|
|
tvga->accel.src = tvga->accel.src_old = tvga->accel.src_x + (tvga->accel.src_y * tvga->accel.pitch);
|
|
tvga->accel.dst = tvga->accel.dst_old = tvga->accel.dst_x + (tvga->accel.dst_y * tvga->accel.pitch);
|
|
tvga->accel.pat_x = tvga->accel.dst_x;
|
|
tvga->accel.pat_y = tvga->accel.dst_y;
|
|
}
|
|
|
|
switch (tvga->accel.flags & (TGUI_SRCMONO|TGUI_SRCDISP))
|
|
{
|
|
case TGUI_SRCCPU:
|
|
if (count == -1)
|
|
{
|
|
// pclog("Blit start TGUI_SRCCPU\n");
|
|
if (svga->crtc[0x21] & 0x20)
|
|
mem_mapping_set_handler(&tvga->linear_mapping, svga_read_linear, svga_readw_linear, svga_readl_linear, tvga_accel_write_fb_b, tvga_accel_write_fb_w, tvga_accel_write_fb_l);
|
|
|
|
if (tvga->accel.use_src)
|
|
return;
|
|
}
|
|
else
|
|
count >>= 3;
|
|
// pclog("TGUI_SRCCPU\n");
|
|
while (count)
|
|
{
|
|
if (tvga->accel.bpp == 0)
|
|
{
|
|
src_dat = cpu_dat >> 24;
|
|
cpu_dat <<= 8;
|
|
}
|
|
else
|
|
{
|
|
src_dat = (cpu_dat >> 24) | ((cpu_dat >> 8) & 0xff00);
|
|
cpu_dat <<= 16;
|
|
count--;
|
|
}
|
|
READ(tvga->accel.dst, dst_dat);
|
|
pat_dat = tvga->accel.tvga_pattern[tvga->accel.pat_y & 7][tvga->accel.pat_x & 7];
|
|
|
|
if (!(tvga->accel.flags & TGUI_TRANSENA) || src_dat != trans_col)
|
|
{
|
|
MIX();
|
|
|
|
WRITE(tvga->accel.dst, out);
|
|
}
|
|
|
|
// pclog(" %i,%i %02X %02X %02X %02X\n", tvga->accel.x, tvga->accel.y, src_dat,dst_dat,pat_dat, out);
|
|
|
|
tvga->accel.src += xdir;
|
|
tvga->accel.dst += xdir;
|
|
tvga->accel.pat_x += xdir;
|
|
|
|
tvga->accel.x++;
|
|
if (tvga->accel.x > tvga->accel.size_x)
|
|
{
|
|
tvga->accel.x = 0;
|
|
tvga->accel.y++;
|
|
|
|
tvga->accel.pat_x = tvga->accel.dst_x;
|
|
|
|
tvga->accel.src = tvga->accel.src_old = tvga->accel.src_old + (ydir * tvga->accel.pitch);
|
|
tvga->accel.dst = tvga->accel.dst_old = tvga->accel.dst_old + (ydir * tvga->accel.pitch);
|
|
tvga->accel.pat_y += ydir;
|
|
|
|
if (tvga->accel.y > tvga->accel.size_y)
|
|
{
|
|
if (svga->crtc[0x21] & 0x20)
|
|
{
|
|
// pclog("Blit end\n");
|
|
mem_mapping_set_handler(&tvga->linear_mapping, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear);
|
|
}
|
|
return;
|
|
}
|
|
if (tvga->accel.use_src)
|
|
return;
|
|
}
|
|
count--;
|
|
}
|
|
break;
|
|
|
|
case TGUI_SRCMONO | TGUI_SRCCPU:
|
|
if (count == -1)
|
|
{
|
|
// pclog("Blit start TGUI_SRCMONO | TGUI_SRCCPU\n");
|
|
if (svga->crtc[0x21] & 0x20)
|
|
mem_mapping_set_handler(&tvga->linear_mapping, svga_read_linear, svga_readw_linear, svga_readl_linear, tvga_accel_write_fb_b, tvga_accel_write_fb_w, tvga_accel_write_fb_l);
|
|
|
|
// pclog(" %i\n", tvga->accel.command);
|
|
if (tvga->accel.use_src)
|
|
return;
|
|
}
|
|
// pclog("TGUI_SRCMONO | TGUI_SRCCPU\n");
|
|
while (count)
|
|
{
|
|
src_dat = ((cpu_dat >> 31) ? tvga->accel.fg_col : tvga->accel.bg_col);
|
|
if (tvga->accel.bpp == 0)
|
|
src_dat &= 0xff;
|
|
|
|
READ(tvga->accel.dst, dst_dat);
|
|
pat_dat = tvga->accel.tvga_pattern[tvga->accel.pat_y & 7][tvga->accel.pat_x & 7];
|
|
|
|
if (!(tvga->accel.flags & TGUI_TRANSENA) || src_dat != trans_col)
|
|
{
|
|
MIX();
|
|
|
|
WRITE(tvga->accel.dst, out);
|
|
}
|
|
// pclog(" %i,%i %02X %02X %02X %02X %i\n", tvga->accel.x, tvga->accel.y, src_dat,dst_dat,pat_dat, out, (!(tvga->accel.flags & TGUI_TRANSENA) || src_dat != trans_col));
|
|
cpu_dat <<= 1;
|
|
tvga->accel.src += xdir;
|
|
tvga->accel.dst += xdir;
|
|
tvga->accel.pat_x += xdir;
|
|
|
|
tvga->accel.x++;
|
|
if (tvga->accel.x > tvga->accel.size_x)
|
|
{
|
|
tvga->accel.x = 0;
|
|
tvga->accel.y++;
|
|
|
|
tvga->accel.pat_x = tvga->accel.dst_x;
|
|
|
|
tvga->accel.src = tvga->accel.src_old = tvga->accel.src_old + (ydir * tvga->accel.pitch);
|
|
tvga->accel.dst = tvga->accel.dst_old = tvga->accel.dst_old + (ydir * tvga->accel.pitch);
|
|
tvga->accel.pat_y += ydir;
|
|
|
|
if (tvga->accel.y > tvga->accel.size_y)
|
|
{
|
|
if (svga->crtc[0x21] & 0x20)
|
|
{
|
|
// pclog("Blit end\n");
|
|
mem_mapping_set_handler(&tvga->linear_mapping, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear);
|
|
}
|
|
return;
|
|
}
|
|
if (tvga->accel.use_src)
|
|
return;
|
|
}
|
|
count--;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
while (count)
|
|
{
|
|
READ(tvga->accel.src, src_dat);
|
|
READ(tvga->accel.dst, dst_dat);
|
|
pat_dat = tvga->accel.tvga_pattern[tvga->accel.pat_y & 7][tvga->accel.pat_x & 7];
|
|
|
|
if (!(tvga->accel.flags & TGUI_TRANSENA) || src_dat != trans_col)
|
|
{
|
|
MIX();
|
|
|
|
WRITE(tvga->accel.dst, out);
|
|
}
|
|
// pclog(" %i,%i %02X %02X %02X %02X\n", tvga->accel.x, tvga->accel.y, src_dat,dst_dat,pat_dat, out);
|
|
|
|
tvga->accel.src += xdir;
|
|
tvga->accel.dst += xdir;
|
|
tvga->accel.pat_x += xdir;
|
|
|
|
tvga->accel.x++;
|
|
if (tvga->accel.x > tvga->accel.size_x)
|
|
{
|
|
tvga->accel.x = 0;
|
|
tvga->accel.y++;
|
|
|
|
tvga->accel.pat_x = tvga->accel.dst_x;
|
|
|
|
tvga->accel.src = tvga->accel.src_old = tvga->accel.src_old + (ydir * tvga->accel.pitch);
|
|
tvga->accel.dst = tvga->accel.dst_old = tvga->accel.dst_old + (ydir * tvga->accel.pitch);
|
|
tvga->accel.pat_y += ydir;
|
|
|
|
if (tvga->accel.y > tvga->accel.size_y)
|
|
return;
|
|
}
|
|
count--;
|
|
}
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
void tvga_accel_write(uint32_t addr, uint8_t val, void *p)
|
|
{
|
|
tvga_t *tvga = (tvga_t *)p;
|
|
// pclog("tvga_accel_write : %08X %02X %04X(%08X):%08X %02X\n", addr, val, CS,cs,pc, opcode);
|
|
if ((addr & ~0xff) != 0xbff00)
|
|
return;
|
|
switch (addr & 0xff)
|
|
{
|
|
case 0x22:
|
|
tvga->accel.ger22 = val;
|
|
tvga->accel.pitch = 512 << ((val >> 2) & 3);
|
|
tvga->accel.bpp = (val & 3) ? 1 : 0;
|
|
tvga->accel.pitch >>= tvga->accel.bpp;
|
|
break;
|
|
|
|
case 0x24: /*Command*/
|
|
tvga->accel.command = val;
|
|
tvga_accel_command(-1, 0, tvga);
|
|
break;
|
|
|
|
case 0x27: /*ROP*/
|
|
tvga->accel.rop = val;
|
|
tvga->accel.use_src = (val & 0x33) ^ ((val >> 2) & 0x33);
|
|
pclog("Write ROP %02X %i\n", val, tvga->accel.use_src);
|
|
break;
|
|
|
|
case 0x28: /*Flags*/
|
|
tvga->accel.flags = (tvga->accel.flags & 0xff00) | val;
|
|
break;
|
|
case 0x29: /*Flags*/
|
|
tvga->accel.flags = (tvga->accel.flags & 0xff) | (val << 8);
|
|
break;
|
|
|
|
case 0x2b:
|
|
tvga->accel.offset = val & 7;
|
|
break;
|
|
|
|
case 0x2c: /*Foreground colour*/
|
|
tvga->accel.fg_col = (tvga->accel.fg_col & 0xff00) | val;
|
|
break;
|
|
case 0x2d: /*Foreground colour*/
|
|
tvga->accel.fg_col = (tvga->accel.fg_col & 0xff) | (val << 8);
|
|
break;
|
|
|
|
case 0x30: /*Background colour*/
|
|
tvga->accel.bg_col = (tvga->accel.bg_col & 0xff00) | val;
|
|
break;
|
|
case 0x31: /*Background colour*/
|
|
tvga->accel.bg_col = (tvga->accel.bg_col & 0xff) | (val << 8);
|
|
break;
|
|
|
|
case 0x38: /*Dest X*/
|
|
tvga->accel.dst_x = (tvga->accel.dst_x & 0xff00) | val;
|
|
break;
|
|
case 0x39: /*Dest X*/
|
|
tvga->accel.dst_x = (tvga->accel.dst_x & 0xff) | (val << 8);
|
|
break;
|
|
case 0x3a: /*Dest Y*/
|
|
tvga->accel.dst_y = (tvga->accel.dst_y & 0xff00) | val;
|
|
break;
|
|
case 0x3b: /*Dest Y*/
|
|
tvga->accel.dst_y = (tvga->accel.dst_y & 0xff) | (val << 8);
|
|
break;
|
|
|
|
case 0x3c: /*Src X*/
|
|
tvga->accel.src_x = (tvga->accel.src_x & 0xff00) | val;
|
|
break;
|
|
case 0x3d: /*Src X*/
|
|
tvga->accel.src_x = (tvga->accel.src_x & 0xff) | (val << 8);
|
|
break;
|
|
case 0x3e: /*Src Y*/
|
|
tvga->accel.src_y = (tvga->accel.src_y & 0xff00) | val;
|
|
break;
|
|
case 0x3f: /*Src Y*/
|
|
tvga->accel.src_y = (tvga->accel.src_y & 0xff) | (val << 8);
|
|
break;
|
|
|
|
case 0x40: /*Size X*/
|
|
tvga->accel.size_x = (tvga->accel.size_x & 0xff00) | val;
|
|
break;
|
|
case 0x41: /*Size X*/
|
|
tvga->accel.size_x = (tvga->accel.size_x & 0xff) | (val << 8);
|
|
break;
|
|
case 0x42: /*Size Y*/
|
|
tvga->accel.size_y = (tvga->accel.size_y & 0xff00) | val;
|
|
break;
|
|
case 0x43: /*Size Y*/
|
|
tvga->accel.size_y = (tvga->accel.size_y & 0xff) | (val << 8);
|
|
break;
|
|
|
|
case 0x80: case 0x81: case 0x82: case 0x83:
|
|
case 0x84: case 0x85: case 0x86: case 0x87:
|
|
case 0x88: case 0x89: case 0x8a: case 0x8b:
|
|
case 0x8c: case 0x8d: case 0x8e: case 0x8f:
|
|
case 0x90: case 0x91: case 0x92: case 0x93:
|
|
case 0x94: case 0x95: case 0x96: case 0x97:
|
|
case 0x98: case 0x99: case 0x9a: case 0x9b:
|
|
case 0x9c: case 0x9d: case 0x9e: case 0x9f:
|
|
case 0xa0: case 0xa1: case 0xa2: case 0xa3:
|
|
case 0xa4: case 0xa5: case 0xa6: case 0xa7:
|
|
case 0xa8: case 0xa9: case 0xaa: case 0xab:
|
|
case 0xac: case 0xad: case 0xae: case 0xaf:
|
|
case 0xb0: case 0xb1: case 0xb2: case 0xb3:
|
|
case 0xb4: case 0xb5: case 0xb6: case 0xb7:
|
|
case 0xb8: case 0xb9: case 0xba: case 0xbb:
|
|
case 0xbc: case 0xbd: case 0xbe: case 0xbf:
|
|
case 0xc0: case 0xc1: case 0xc2: case 0xc3:
|
|
case 0xc4: case 0xc5: case 0xc6: case 0xc7:
|
|
case 0xc8: case 0xc9: case 0xca: case 0xcb:
|
|
case 0xcc: case 0xcd: case 0xce: case 0xcf:
|
|
case 0xd0: case 0xd1: case 0xd2: case 0xd3:
|
|
case 0xd4: case 0xd5: case 0xd6: case 0xd7:
|
|
case 0xd8: case 0xd9: case 0xda: case 0xdb:
|
|
case 0xdc: case 0xdd: case 0xde: case 0xdf:
|
|
case 0xe0: case 0xe1: case 0xe2: case 0xe3:
|
|
case 0xe4: case 0xe5: case 0xe6: case 0xe7:
|
|
case 0xe8: case 0xe9: case 0xea: case 0xeb:
|
|
case 0xec: case 0xed: case 0xee: case 0xef:
|
|
case 0xf0: case 0xf1: case 0xf2: case 0xf3:
|
|
case 0xf4: case 0xf5: case 0xf6: case 0xf7:
|
|
case 0xf8: case 0xf9: case 0xfa: case 0xfb:
|
|
case 0xfc: case 0xfd: case 0xfe: case 0xff:
|
|
tvga->accel.pattern[addr & 0x7f] = val;
|
|
break;
|
|
}
|
|
}
|
|
|
|
void tvga_accel_write_w(uint32_t addr, uint16_t val, void *p)
|
|
{
|
|
tvga_t *tvga = (tvga_t *)p;
|
|
// pclog("tvga_accel_write_w %08X %04X\n", addr, val);
|
|
tvga_accel_write(addr, val, tvga);
|
|
tvga_accel_write(addr + 1, val >> 8, tvga);
|
|
}
|
|
|
|
void tvga_accel_write_l(uint32_t addr, uint32_t val, void *p)
|
|
{
|
|
tvga_t *tvga = (tvga_t *)p;
|
|
// pclog("tvga_accel_write_l %08X %08X\n", addr, val);
|
|
tvga_accel_write(addr, val, tvga);
|
|
tvga_accel_write(addr + 1, val >> 8, tvga);
|
|
tvga_accel_write(addr + 2, val >> 16, tvga);
|
|
tvga_accel_write(addr + 3, val >> 24, tvga);
|
|
}
|
|
|
|
uint8_t tvga_accel_read(uint32_t addr, void *p)
|
|
{
|
|
tvga_t *tvga = (tvga_t *)p;
|
|
// pclog("tvga_accel_read : %08X\n", addr);
|
|
if ((addr & ~0xff) != 0xbff00)
|
|
return 0xff;
|
|
switch (addr & 0xff)
|
|
{
|
|
case 0x20: /*Status*/
|
|
return 0;
|
|
|
|
case 0x27: /*ROP*/
|
|
return tvga->accel.rop;
|
|
|
|
case 0x28: /*Flags*/
|
|
return tvga->accel.flags & 0xff;
|
|
case 0x29: /*Flags*/
|
|
return tvga->accel.flags >> 8;
|
|
|
|
case 0x2b:
|
|
return tvga->accel.offset;
|
|
|
|
case 0x2c: /*Background colour*/
|
|
return tvga->accel.bg_col & 0xff;
|
|
case 0x2d: /*Background colour*/
|
|
return tvga->accel.bg_col >> 8;
|
|
|
|
case 0x30: /*Foreground colour*/
|
|
return tvga->accel.fg_col & 0xff;
|
|
case 0x31: /*Foreground colour*/
|
|
return tvga->accel.fg_col >> 8;
|
|
|
|
case 0x38: /*Dest X*/
|
|
return tvga->accel.dst_x & 0xff;
|
|
case 0x39: /*Dest X*/
|
|
return tvga->accel.dst_x >> 8;
|
|
case 0x3a: /*Dest Y*/
|
|
return tvga->accel.dst_y & 0xff;
|
|
case 0x3b: /*Dest Y*/
|
|
return tvga->accel.dst_y >> 8;
|
|
|
|
case 0x3c: /*Src X*/
|
|
return tvga->accel.src_x & 0xff;
|
|
case 0x3d: /*Src X*/
|
|
return tvga->accel.src_x >> 8;
|
|
case 0x3e: /*Src Y*/
|
|
return tvga->accel.src_y & 0xff;
|
|
case 0x3f: /*Src Y*/
|
|
return tvga->accel.src_y >> 8;
|
|
|
|
case 0x40: /*Size X*/
|
|
return tvga->accel.size_x & 0xff;
|
|
case 0x41: /*Size X*/
|
|
return tvga->accel.size_x >> 8;
|
|
case 0x42: /*Size Y*/
|
|
return tvga->accel.size_y & 0xff;
|
|
case 0x43: /*Size Y*/
|
|
return tvga->accel.size_y >> 8;
|
|
|
|
case 0x80: case 0x81: case 0x82: case 0x83:
|
|
case 0x84: case 0x85: case 0x86: case 0x87:
|
|
case 0x88: case 0x89: case 0x8a: case 0x8b:
|
|
case 0x8c: case 0x8d: case 0x8e: case 0x8f:
|
|
case 0x90: case 0x91: case 0x92: case 0x93:
|
|
case 0x94: case 0x95: case 0x96: case 0x97:
|
|
case 0x98: case 0x99: case 0x9a: case 0x9b:
|
|
case 0x9c: case 0x9d: case 0x9e: case 0x9f:
|
|
case 0xa0: case 0xa1: case 0xa2: case 0xa3:
|
|
case 0xa4: case 0xa5: case 0xa6: case 0xa7:
|
|
case 0xa8: case 0xa9: case 0xaa: case 0xab:
|
|
case 0xac: case 0xad: case 0xae: case 0xaf:
|
|
case 0xb0: case 0xb1: case 0xb2: case 0xb3:
|
|
case 0xb4: case 0xb5: case 0xb6: case 0xb7:
|
|
case 0xb8: case 0xb9: case 0xba: case 0xbb:
|
|
case 0xbc: case 0xbd: case 0xbe: case 0xbf:
|
|
case 0xc0: case 0xc1: case 0xc2: case 0xc3:
|
|
case 0xc4: case 0xc5: case 0xc6: case 0xc7:
|
|
case 0xc8: case 0xc9: case 0xca: case 0xcb:
|
|
case 0xcc: case 0xcd: case 0xce: case 0xcf:
|
|
case 0xd0: case 0xd1: case 0xd2: case 0xd3:
|
|
case 0xd4: case 0xd5: case 0xd6: case 0xd7:
|
|
case 0xd8: case 0xd9: case 0xda: case 0xdb:
|
|
case 0xdc: case 0xdd: case 0xde: case 0xdf:
|
|
case 0xe0: case 0xe1: case 0xe2: case 0xe3:
|
|
case 0xe4: case 0xe5: case 0xe6: case 0xe7:
|
|
case 0xe8: case 0xe9: case 0xea: case 0xeb:
|
|
case 0xec: case 0xed: case 0xee: case 0xef:
|
|
case 0xf0: case 0xf1: case 0xf2: case 0xf3:
|
|
case 0xf4: case 0xf5: case 0xf6: case 0xf7:
|
|
case 0xf8: case 0xf9: case 0xfa: case 0xfb:
|
|
case 0xfc: case 0xfd: case 0xfe: case 0xff:
|
|
return tvga->accel.pattern[addr & 0x7f];
|
|
}
|
|
return 0xff;
|
|
}
|
|
|
|
uint16_t tvga_accel_read_w(uint32_t addr, void *p)
|
|
{
|
|
tvga_t *tvga = (tvga_t *)p;
|
|
// pclog("tvga_accel_read_w %08X\n", addr);
|
|
return tvga_accel_read(addr, tvga) | (tvga_accel_read(addr + 1, tvga) << 8);
|
|
}
|
|
|
|
uint32_t tvga_accel_read_l(uint32_t addr, void *p)
|
|
{
|
|
tvga_t *tvga = (tvga_t *)p;
|
|
// pclog("tvga_accel_read_l %08X\n", addr);
|
|
return tvga_accel_read_w(addr, tvga) | (tvga_accel_read_w(addr + 2, tvga) << 16);
|
|
}
|
|
|
|
void tvga_accel_write_fb_b(uint32_t addr, uint8_t val, void *p)
|
|
{
|
|
svga_t *svga = (svga_t *)p;
|
|
tvga_t *tvga = (tvga_t *)svga->p;
|
|
// pclog("tvga_accel_write_fb_b %08X %02X\n", addr, val);
|
|
tvga_accel_command(8, val << 24, tvga);
|
|
}
|
|
|
|
void tvga_accel_write_fb_w(uint32_t addr, uint16_t val, void *p)
|
|
{
|
|
svga_t *svga = (svga_t *)p;
|
|
tvga_t *tvga = (tvga_t *)svga->p;
|
|
// pclog("tvga_accel_write_fb_w %08X %04X\n", addr, val);
|
|
tvga_accel_command(16, (((val & 0xff00) >> 8) | ((val & 0x00ff) << 8)) << 16, tvga);
|
|
}
|
|
|
|
void tvga_accel_write_fb_l(uint32_t addr, uint32_t val, void *p)
|
|
{
|
|
svga_t *svga = (svga_t *)p;
|
|
tvga_t *tvga = (tvga_t *)svga->p;
|
|
// pclog("tvga_accel_write_fb_l %08X %08X\n", addr, val);
|
|
tvga_accel_command(32, ((val & 0xff000000) >> 24) | ((val & 0x00ff0000) >> 8) | ((val & 0x0000ff00) << 8) | ((val & 0x000000ff) << 24), tvga);
|
|
}
|