189 lines
7.5 KiB
C
189 lines
7.5 KiB
C
#include "ibm.h"
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#include "cpu.h"
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#include "io.h"
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#include "mem.h"
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#include "model.h"
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#include "pit.h"
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#include "timer.h"
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#include "x86.h"
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#include "intel.h"
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static uint8_t batman_port_92;
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uint8_t batman_brdconfig(uint16_t port, void *p)
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{
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// pclog("batman_brdconfig read port=%04x\n", port);
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switch (port)
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{
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case 0x73:
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return 0xff;
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case 0x75:
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return 0xdf;
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case 0x92:
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return batman_port_92;
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}
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return 0;
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}
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void batman_brdconfig_write(uint16_t port, uint8_t val, void *p)
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{
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switch (port)
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{
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case 0x92:
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if ((mem_a20_alt ^ val) & 2)
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{
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mem_a20_alt = val & 2;
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mem_a20_recalc();
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}
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if ((~batman_port_92 & val) & 1)
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{
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softresetx86();
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cpu_set_edx();
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}
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batman_port_92 = val;
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}
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}
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static uint16_t batman_timer_latch;
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static pc_timer_t batman_timer;
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static void batman_timer_over(void *p)
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{
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}
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static void batman_timer_write(uint16_t addr, uint8_t val, void *p)
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{
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if (addr & 1)
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batman_timer_latch = (batman_timer_latch & 0xff) | (val << 8);
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else
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batman_timer_latch = (batman_timer_latch & 0xff00) | val;
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timer_set_delay_u64(&batman_timer, batman_timer_latch * TIMER_USEC);
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}
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static uint8_t batman_timer_read(uint16_t addr, void *p)
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{
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uint16_t batman_timer_latch;
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cycles -= (int)(PITCONST >> 32);
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batman_timer_latch = timer_get_remaining_us(&batman_timer);
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if (addr & 1)
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return batman_timer_latch >> 8;
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return batman_timer_latch & 0xff;
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}
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void intel_batman_init()
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{
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io_sethandler(0x0073, 0x0001, batman_brdconfig, NULL, NULL, NULL, NULL, NULL, NULL);
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io_sethandler(0x0075, 0x0001, batman_brdconfig, NULL, NULL, NULL, NULL, NULL, NULL);
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io_sethandler(0x0078, 0x0002, batman_timer_read, NULL, NULL, batman_timer_write, NULL, NULL, NULL);
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io_sethandler(0x0092, 0x0001, batman_brdconfig, NULL, NULL, batman_brdconfig_write, NULL, NULL, NULL);
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batman_port_92 = 0;
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timer_add(&batman_timer, batman_timer_over, NULL, 0);
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}
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uint8_t endeavor_brdconfig(uint16_t port, void *p)
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{
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uint8_t temp;
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CPU *cpu_s = &models[model].cpu[cpu_manufacturer].cpus[cpu];
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// pclog("endeavor_brdconfig read port=%04x\n", port);
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switch (port)
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{
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case 0x79:
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// Bit # | Description | Bit = 1 | Bit = 0
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// 0 | Internal CPU Clock Freq. (Switch 6) | 3/2x | 2x (Manual has these swapped in one place?)
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// 1 | Soft Off capable power supply | No | Yes
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// 2 | On-board Audio present | Yes | No
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// 3 | External CPU clock (Switch 7) | |
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// 4 | External CPU clock (Switch 8) | |
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// 5 | Setup Disable (Switch 5) | Enable access | Disable access
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// 6 | Clear CMOS (Switch 4) | Keep values | Clear values
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// 7 | Password Clear (Switch 3) | Keep password | Clear password
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// Bus Speed | Switch 7 | Switch 8
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// 50 MHz | Off | Off
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// 60 Mhz | On | Off
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// 66 MHz | Off | On
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// Multiplier for each supported processor-
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// -The 3/2 setting is used for 75 MHz, 90 MHz, and 100 MHz processors
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// -The 2 times setting is used for 120 MHz processors.
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if (cpu_s->rspeed == 75000000 && cpu_s->pci_speed == 25000000)
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temp = 0x01;
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else if (cpu_s->rspeed == 90000000 && cpu_s->pci_speed == 30000000)
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temp = 0x01 | 0x08;
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else if (cpu_s->rspeed == 100000000 && cpu_s->pci_speed == 25000000)
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temp = 0x00;
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else if (cpu_s->rspeed == 100000000 && cpu_s->pci_speed == 33333333)
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temp = 0x01 | 0x10;
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else if (cpu_s->rspeed == 120000000 && cpu_s->pci_speed == 30000000)
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temp = 0x08;
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else if (cpu_s->rspeed == 133333333 && cpu_s->pci_speed == 33333333)
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temp = 0x10;
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else
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temp = 0x10; // TODO: how are the overdrive processors configured?
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return 0xe2 | temp;
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}
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return 0;
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}
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void intel_endeavor_init()
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{
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io_sethandler(0x0079, 0x0001, endeavor_brdconfig, NULL, NULL, NULL, NULL, NULL, NULL);
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}
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static uint8_t zappa_brdconfig(uint16_t port, void *p)
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{
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uint8_t temp;
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CPU *cpu_s = &models[model].cpu[cpu_manufacturer].cpus[cpu];
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// pclog("zappa_brdconfig read port=%04x\n", port);
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switch (port)
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{
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case 0x79:
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// Bit # | Description | Bit = 1 | Bit = 0
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// 0 | Internal CPU Clock Freq. (Switch 6) | 3/2x | 2x (Manual has these swapped in one place?)
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// 1 | No Connect | |
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// 2 | No Connect | |
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// 3 | External CPU clock (Switch 7) | |
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// 4 | External CPU clock (Switch 8) | |
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// 5 | Setup Disable (Switch 5) | Enable access | Disable access
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// 6 | Clear CMOS (Switch 4) | Keep values | Clear values
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// 7 | Password Clear (Switch 3) | Keep password | Clear password
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// Bus Speed | Switch 7 | Switch 8
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// 50 MHz | Off | Off
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// 60 Mhz | On | Off
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// 66 MHz | Off | On
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// Multiplier for each supported processor-
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// -The 3/2 setting is used for 75 MHz, 90 MHz, and 100 MHz processors
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// -The 2 times setting is used for 120 MHz processors.
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if (cpu_s->rspeed == 75000000 && cpu_s->pci_speed == 25000000)
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temp = 0x01;
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else if (cpu_s->rspeed == 90000000 && cpu_s->pci_speed == 30000000)
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temp = 0x01 | 0x08;
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else if (cpu_s->rspeed == 100000000 && cpu_s->pci_speed == 25000000)
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temp = 0x00;
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else if (cpu_s->rspeed == 100000000 && cpu_s->pci_speed == 33333333)
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temp = 0x01 | 0x10;
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else if (cpu_s->rspeed == 120000000 && cpu_s->pci_speed == 30000000)
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temp = 0x08;
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else if (cpu_s->rspeed == 133333333 && cpu_s->pci_speed == 33333333)
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temp = 0x10;
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else
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temp = 0x10; // TODO: how are the overdrive processors configured?
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return 0xe0 | temp;
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}
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return 0;
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}
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void intel_zappa_init()
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{
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io_sethandler(0x0079, 0x0001, zappa_brdconfig, NULL, NULL, NULL, NULL, NULL, NULL);
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}
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