120 lines
4.2 KiB
C
120 lines
4.2 KiB
C
/*CS8230 CHIPSet consists of :
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82c301 bus controller
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82c302 page/interleave memory controller
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82a303 high address buffer
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82a304 low address buffer
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82b305 data buffer
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82a306 control buffer*/
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#include "ibm.h"
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#include "cs8230.h"
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#include "io.h"
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#include "mem.h"
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static struct
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{
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int idx;
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uint8_t regs[256];
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} cs8230;
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static void shadow_control(uint32_t addr, uint32_t size, int state)
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{
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// pclog("shadow_control: addr=%08x size=%04x state=%02x\n", addr, size, state);
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switch (state)
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{
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case 0x00:
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mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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break;
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case 0x01:
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mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
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break;
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case 0x10:
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mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
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break;
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case 0x11:
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mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
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break;
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}
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flushmmucache_nopc();
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}
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static void rethink_shadow_mappings(void)
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{
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int c;
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for (c = 0; c < 4*8; c++) /*Addresses 40000-bffff in 16k blocks*/
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{
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if (cs8230.regs[0xa + (c >> 3)] & (1 << (c & 7)))
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mem_set_mem_state(0x40000 + c*0x4000, 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL); /*IO channel*/
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else
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mem_set_mem_state(0x40000 + c*0x4000, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); /*System board*/
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}
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for (c = 0; c < 2*8; c++) /*Addresses c0000-fffff in 16k blocks. System board ROM can be mapped here*/
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{
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if (cs8230.regs[0xe + (c >> 3)] & (1 << (c & 7)))
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mem_set_mem_state(0xc0000 + c*0x4000, 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL); /*IO channel*/
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else
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shadow_control(0xc0000 + c*0x4000, 0x4000, (cs8230.regs[9] >> (3-(c >> 2))) & 0x11);
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}
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}
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static uint8_t cs8230_read(uint16_t port, void *p)
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{
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uint8_t ret = 0xff;
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if (port & 1)
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{
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switch (cs8230.idx)
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{
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case 0x04: /*82C301 ID/version*/
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ret = cs8230.regs[cs8230.idx] & ~0xe3;
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break;
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case 0x08: /*82C302 ID/Version*/
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ret = cs8230.regs[cs8230.idx] & ~0xe0;
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break;
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case 0x05: case 0x06: /*82C301 registers*/
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case 0x09: case 0x0a: case 0x0b: case 0x0c: /*82C302 registers*/
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case 0x0d: case 0x0e: case 0x0f:
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case 0x10: case 0x11: case 0x12: case 0x13:
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case 0x28: case 0x29: case 0x2a:
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ret = cs8230.regs[cs8230.idx];
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break;
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}
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}
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return ret;
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}
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static void cs8230_write(uint16_t port, uint8_t val, void *p)
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{
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if (!(port & 1))
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cs8230.idx = val;
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else
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{
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// pclog("cs8230_write: reg=%02x val=%02x\n", cs8230.idx, val);
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cs8230.regs[cs8230.idx] = val;
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switch (cs8230.idx)
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{
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case 0x09: /*RAM/ROM Configuration in boot area*/
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case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f: /*Address maps*/
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rethink_shadow_mappings();
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break;
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}
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}
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}
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void cs8230_init(void)
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{
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memset(&cs8230, 0, sizeof(cs8230));
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io_sethandler(0x0022, 0x0002,
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cs8230_read, NULL, NULL,
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cs8230_write, NULL, NULL,
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NULL);
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if (mem_size > 768)
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{
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mem_mapping_set_addr(&ram_mid_mapping, 0xa0000, mem_size > 1024 ? 0x60000 : 0x20000 + (mem_size - 768) * 1024);
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mem_mapping_set_exec(&ram_mid_mapping, ram + 0xa0000);
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}
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}
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