9dbedefc5f
- Implemented serial & parallel port configuration - Implemented shadow RAM - OTI-067 now configured as on-board device rather than separate card
156 lines
5.5 KiB
C
156 lines
5.5 KiB
C
#include "ibm.h"
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#include "device.h"
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#include "io.h"
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#include "cpu.h"
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#include "lpt.h"
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#include "mem.h"
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#include "serial.h"
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#include "vid_oti067.h"
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#include "acer386sx.h"
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static int acer_index = 0;
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static uint8_t acer_regs[256];
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static uint8_t acer_last_write;
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static int acer_locked;
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static void *acer_oti067;
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void acer386sx_set_oti067(void *oti067)
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{
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acer_oti067 = oti067;
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}
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void acer386sx_write(uint16_t addr, uint8_t val, void *priv)
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{
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if (addr & 1)
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{
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if (acer_locked)
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{
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if (acer_last_write == 0x14 && val == 0x09)
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acer_locked = 0;
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acer_last_write = val;
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return;
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}
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if (acer_index == 0xff && val == 0xff)
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acer_locked = 1;
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else
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{
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pclog("Write ACER reg %02x %02x %08x\n", acer_index, val, cs);
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acer_regs[acer_index] = val;
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switch (acer_index)
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{
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case 0xa:
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switch ((val >> 4) & 3)
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{
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case 0:
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mem_set_mem_state(0xe0000, 0x10000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
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break;
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case 1:
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mem_set_mem_state(0xe0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
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break;
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case 2:
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mem_set_mem_state(0xe0000, 0x10000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
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break;
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case 3:
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mem_set_mem_state(0xe0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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break;
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}
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break;
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case 0xb:
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switch ((val >> 4) & 3)
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{
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case 0:
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mem_set_mem_state(0xf0000, 0x10000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
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break;
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case 1:
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mem_set_mem_state(0xf0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
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break;
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case 2:
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mem_set_mem_state(0xf0000, 0x10000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
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break;
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case 3:
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mem_set_mem_state(0xf0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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break;
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}
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break;
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}
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}
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}
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else
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acer_index = val;
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}
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uint8_t acer386sx_read(uint16_t addr, void *priv)
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{
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if (acer_locked)
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return 0xff;
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if (addr & 1)
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{
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if ((acer_index >= 0xc0 || acer_index == 0x20) && cpu_iscyrix)
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return 0xff; /*Don't conflict with Cyrix config registers*/
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return acer_regs[acer_index];
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}
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else
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return acer_index;
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}
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static uint8_t acer386sx_37f = 0, acer386sx_io = 0;
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void acer386sx_io_write(uint16_t addr, uint8_t val, void *priv)
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{
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switch (addr)
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{
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case 0x37f:
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acer386sx_37f = val;
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if (val & 4)
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oti067_enable_disable(acer_oti067, 0);
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else
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oti067_enable_disable(acer_oti067, 1);
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break;
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case 0x3f3:
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acer386sx_io = val;
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serial1_remove();
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serial2_remove();
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lpt1_remove();
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lpt2_remove();
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switch (val & 3)
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{
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case 0: lpt1_init(0x378); break;
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case 1: lpt1_init(0x3bc); break;
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case 2: lpt1_init(0x278); break;
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}
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if (!(val & 0x04))
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serial1_set(0x3f8, 4);
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if (!(val & 0x08))
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serial2_set(0x2f8, 3);
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break;
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}
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}
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uint8_t acer386sx_io_read(uint16_t addr, void *priv)
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{
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switch (addr)
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{
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case 0x37f:
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return acer386sx_37f;
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case 0x3f3:
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return acer386sx_io;
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}
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return 0xff;
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}
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void acer386sx_init()
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{
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io_sethandler(0x0022, 0x0002, acer386sx_read, NULL, NULL, acer386sx_write, NULL, NULL, NULL);
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io_sethandler(0x037f, 0x0001, acer386sx_io_read, NULL, NULL, acer386sx_io_write, NULL, NULL, NULL);
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io_sethandler(0x03f3, 0x0001, acer386sx_io_read, NULL, NULL, acer386sx_io_write, NULL, NULL, NULL);
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acer386sx_io = 0;
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acer386sx_37f = 0;
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}
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