ab124776a0
Code blocks now have a varying level of granularity in the page and dirty masks. Most blocks have 64-byte granularity, but blocks that are repeatedly modified drop to 1-byte granularity. This reduces the maximum size of the affected block significantly, but reduces recompilation due to data located too close to code. If the block is still marked as dirty, then it is recompiled without any immediate instruction parameters being baked into the recompiled code, instead being fetched from the RAM array as needed. This severely reduces recompilation rates on some SMC-heavy games, eg Duke Nukem 3D, System Shock, Screamer etc, giving a major speedup.
611 lines
28 KiB
C
611 lines
28 KiB
C
#include "ibm.h"
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#include "x86.h"
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#include "x86_flags.h"
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#include "386_common.h"
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#include "codegen.h"
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#include "codegen_ir.h"
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#include "codegen_ops.h"
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#include "codegen_ops_helpers.h"
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#include "codegen_ops_misc.h"
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uint32_t ropLEA_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
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{
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int dest_reg = (fetchdat >> 3) & 7;
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if ((fetchdat & 0xc0) == 0xc0)
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return 0;
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codegen_mark_code_present(block, cs+op_pc, 1);
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codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
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uop_MOV(ir, IREG_16(dest_reg), IREG_eaaddr_W);
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return op_pc + 1;
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}
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uint32_t ropLEA_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
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{
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int dest_reg = (fetchdat >> 3) & 7;
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if ((fetchdat & 0xc0) == 0xc0)
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return 0;
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codegen_mark_code_present(block, cs+op_pc, 1);
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codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
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uop_MOV(ir, IREG_32(dest_reg), IREG_eaaddr);
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return op_pc + 1;
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}
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uint32_t ropF6(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
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{
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x86seg *target_seg = NULL;
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uint8_t imm_data;
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int reg;
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if (fetchdat & 0x20)
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return 0;
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codegen_mark_code_present(block, cs+op_pc, 1);
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if ((fetchdat & 0xc0) == 0xc0)
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reg = IREG_8(fetchdat & 7);
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else
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{
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uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
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target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
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if ((fetchdat & 0x30) == 0x10) /*NEG/NOT*/
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codegen_check_seg_write(block, ir, target_seg);
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else
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codegen_check_seg_read(block, ir, target_seg);
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uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
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reg = IREG_temp0_B;
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}
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switch (fetchdat & 0x38)
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{
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case 0x00: case 0x08: /*TEST*/
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imm_data = fastreadb(cs + op_pc + 1);
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uop_AND_IMM(ir, IREG_flags_res_B, reg, imm_data);
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uop_MOVZX(ir, IREG_flags_res, IREG_flags_res_B);
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uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN8);
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codegen_flags_changed = 1;
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codegen_mark_code_present(block, cs+op_pc+1, 1);
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return op_pc+2;
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case 0x10: /*NOT*/
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uop_XOR_IMM(ir, reg, reg, 0xff);
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if ((fetchdat & 0xc0) != 0xc0)
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uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, reg);
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codegen_flags_changed = 1;
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return op_pc+1;
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case 0x18: /*NEG*/
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uop_MOV_IMM(ir, IREG_temp1_B, 0);
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if ((fetchdat & 0xc0) == 0xc0)
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{
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uop_MOVZX(ir, IREG_flags_op2, reg);
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uop_SUB(ir, IREG_temp1_B, IREG_temp1_B, reg);
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uop_MOVZX(ir, IREG_flags_res, IREG_temp1_B);
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uop_MOV(ir, reg, IREG_temp1_B);
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}
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else
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{
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uop_SUB(ir, IREG_temp1_B, IREG_temp1_B, reg);
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uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_B);
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uop_MOVZX(ir, IREG_flags_op2, IREG_temp0_B);
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uop_MOVZX(ir, IREG_flags_res, IREG_temp1_B);
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}
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uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB8);
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uop_MOV_IMM(ir, IREG_flags_op1, 0);
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codegen_flags_changed = 1;
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return op_pc+1;
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}
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return 0;
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}
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uint32_t ropF7_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
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{
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x86seg *target_seg = NULL;
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uint16_t imm_data;
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int reg;
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if (fetchdat & 0x20)
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return 0;
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codegen_mark_code_present(block, cs+op_pc, 1);
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if ((fetchdat & 0xc0) == 0xc0)
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reg = IREG_16(fetchdat & 7);
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else
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{
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uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
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target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
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if ((fetchdat & 0x30) == 0x10) /*NEG/NOT*/
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codegen_check_seg_write(block, ir, target_seg);
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else
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codegen_check_seg_read(block, ir, target_seg);
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uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
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reg = IREG_temp0_W;
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}
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switch (fetchdat & 0x38)
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{
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case 0x00: case 0x08: /*TEST*/
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imm_data = fastreadw(cs + op_pc + 1);
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uop_AND_IMM(ir, IREG_flags_res_W, reg, imm_data);
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uop_MOVZX(ir, IREG_flags_res, IREG_flags_res_W);
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uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN16);
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codegen_flags_changed = 1;
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codegen_mark_code_present(block, cs+op_pc+1, 2);
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return op_pc+3;
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case 0x10: /*NOT*/
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uop_XOR_IMM(ir, reg, reg, 0xffff);
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if ((fetchdat & 0xc0) != 0xc0)
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uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, reg);
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codegen_flags_changed = 1;
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return op_pc+1;
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case 0x18: /*NEG*/
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uop_MOV_IMM(ir, IREG_temp1_W, 0);
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if ((fetchdat & 0xc0) == 0xc0)
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{
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uop_MOVZX(ir, IREG_flags_op2, reg);
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uop_SUB(ir, IREG_temp1_W, IREG_temp1_W, reg);
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uop_MOVZX(ir, IREG_flags_res, IREG_temp1_W);
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uop_MOV(ir, reg, IREG_temp1_W);
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}
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else
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{
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uop_SUB(ir, IREG_temp1_W, IREG_temp1_W, reg);
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uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_W);
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uop_MOVZX(ir, IREG_flags_op2, IREG_temp0_W);
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uop_MOVZX(ir, IREG_flags_res, IREG_temp1_W);
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}
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uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB16);
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uop_MOV_IMM(ir, IREG_flags_op1, 0);
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codegen_flags_changed = 1;
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return op_pc+1;
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}
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return 0;
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}
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uint32_t ropF7_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
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{
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x86seg *target_seg = NULL;
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uint32_t imm_data;
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int reg;
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if (fetchdat & 0x20)
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return 0;
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codegen_mark_code_present(block, cs+op_pc, 1);
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if ((fetchdat & 0xc0) == 0xc0)
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reg = IREG_32(fetchdat & 7);
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else
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{
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uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
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target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
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if ((fetchdat & 0x30) == 0x10) /*NEG/NOT*/
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codegen_check_seg_write(block, ir, target_seg);
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else
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codegen_check_seg_read(block, ir, target_seg);
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uop_MEM_LOAD_REG(ir, IREG_temp0, ireg_seg_base(target_seg), IREG_eaaddr);
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reg = IREG_temp0;
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}
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switch (fetchdat & 0x38)
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{
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case 0x00: case 0x08: /*TEST*/
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imm_data = fastreadl(cs + op_pc + 1);
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uop_AND_IMM(ir, IREG_flags_res, reg, imm_data);
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uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN32);
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codegen_flags_changed = 1;
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codegen_mark_code_present(block, cs+op_pc+1, 4);
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return op_pc+5;
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case 0x10: /*NOT*/
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uop_XOR_IMM(ir, reg, reg, 0xffffffff);
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if ((fetchdat & 0xc0) != 0xc0)
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uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, reg);
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codegen_flags_changed = 1;
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return op_pc+1;
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case 0x18: /*NEG*/
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uop_MOV_IMM(ir, IREG_temp1, 0);
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if ((fetchdat & 0xc0) == 0xc0)
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{
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uop_MOV(ir, IREG_flags_op2, reg);
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uop_SUB(ir, IREG_temp1, IREG_temp1, reg);
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uop_MOV(ir, IREG_flags_res, IREG_temp1);
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uop_MOV(ir, reg, IREG_temp1);
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}
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else
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{
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uop_SUB(ir, IREG_temp1, IREG_temp1, reg);
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uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1);
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uop_MOV(ir, IREG_flags_op2, IREG_temp0);
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uop_MOV(ir, IREG_flags_res, IREG_temp1);
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}
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uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB32);
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uop_MOV_IMM(ir, IREG_flags_op1, 0);
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codegen_flags_changed = 1;
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return op_pc+1;
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}
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return 0;
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}
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static void rebuild_c(ir_data_t *ir)
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{
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int needs_rebuild = 1;
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if (codegen_flags_changed)
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{
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switch (cpu_state.flags_op)
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{
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case FLAGS_INC8: case FLAGS_INC16: case FLAGS_INC32:
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case FLAGS_DEC8: case FLAGS_DEC16: case FLAGS_DEC32:
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needs_rebuild = 0;
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break;
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}
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}
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if (needs_rebuild)
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{
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uop_CALL_FUNC(ir, flags_rebuild_c);
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}
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}
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uint32_t ropFF_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
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{
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x86seg *target_seg = NULL;
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int src_reg, sp_reg;
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if ((fetchdat & 0x38) != 0x00 && (fetchdat & 0x38) != 0x08 && (fetchdat & 0x38) != 0x10 && (fetchdat & 0x38) != 0x20 && (fetchdat & 0x38) != 0x28 && (fetchdat & 0x38) != 0x30)
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return 0;
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codegen_mark_code_present(block, cs+op_pc, 1);
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if ((fetchdat & 0xc0) == 0xc0)
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{
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if ((fetchdat & 0x38) == 0x28)
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return 0;
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src_reg = IREG_16(fetchdat & 7);
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}
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else
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{
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uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
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target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
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if (!(fetchdat & 0x30)) /*INC/DEC*/
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codegen_check_seg_write(block, ir, target_seg);
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else
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codegen_check_seg_read(block, ir, target_seg);
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uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
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src_reg = IREG_temp0_W;
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}
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switch (fetchdat & 0x38)
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{
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case 0x00: /*INC*/
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rebuild_c(ir);
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codegen_flags_changed = 1;
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if ((fetchdat & 0xc0) == 0xc0)
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{
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uop_MOVZX(ir, IREG_flags_op1, src_reg);
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uop_ADD_IMM(ir, src_reg, src_reg, 1);
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uop_MOVZX(ir, IREG_flags_res, src_reg);
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uop_MOV_IMM(ir, IREG_flags_op2, 1);
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uop_MOV_IMM(ir, IREG_flags_op, FLAGS_INC16);
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}
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else
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{
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uop_ADD_IMM(ir, IREG_temp1_W, src_reg, 1);
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uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_W);
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uop_MOVZX(ir, IREG_flags_op1, src_reg);
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uop_MOVZX(ir, IREG_flags_res, IREG_temp1_W);
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uop_MOV_IMM(ir, IREG_flags_op2, 1);
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uop_MOV_IMM(ir, IREG_flags_op, FLAGS_INC16);
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}
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return op_pc+1;
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case 0x08: /*DEC*/
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rebuild_c(ir);
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codegen_flags_changed = 1;
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if ((fetchdat & 0xc0) == 0xc0)
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{
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uop_MOVZX(ir, IREG_flags_op1, src_reg);
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uop_SUB_IMM(ir, src_reg, src_reg, 1);
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uop_MOVZX(ir, IREG_flags_res, src_reg);
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uop_MOV_IMM(ir, IREG_flags_op2, 1);
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uop_MOV_IMM(ir, IREG_flags_op, FLAGS_DEC16);
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}
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else
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{
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uop_SUB_IMM(ir, IREG_temp1_W, src_reg, 1);
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uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_W);
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uop_MOVZX(ir, IREG_flags_op1, src_reg);
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uop_MOVZX(ir, IREG_flags_res, IREG_temp1_W);
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uop_MOV_IMM(ir, IREG_flags_op2, 1);
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uop_MOV_IMM(ir, IREG_flags_op, FLAGS_DEC16);
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}
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return op_pc+1;
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case 0x10: /*CALL*/
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if ((fetchdat & 0xc0) == 0xc0)
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uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
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sp_reg = LOAD_SP_WITH_OFFSET(ir, -2);
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uop_MEM_STORE_IMM_16(ir, IREG_SS_base, sp_reg, op_pc + 1);
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SUB_SP(ir, 2);
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uop_MOVZX(ir, IREG_pc, src_reg);
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return -1;
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case 0x20: /*JMP*/
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uop_MOVZX(ir, IREG_pc, src_reg);
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return -1;
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case 0x28: /*JMP far*/
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uop_MEM_LOAD_REG_OFFSET(ir, IREG_temp1_W, ireg_seg_base(target_seg), IREG_eaaddr, 2);
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uop_LOAD_FUNC_ARG_REG(ir, 0, IREG_temp1_W);
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uop_LOAD_FUNC_ARG_IMM(ir, 1, cpu_state.oldpc);
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uop_CALL_FUNC(ir, loadcsjmp);
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uop_MOVZX(ir, IREG_pc, src_reg);
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return -1;
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case 0x30: /*PUSH*/
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if ((fetchdat & 0xc0) == 0xc0)
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uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
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sp_reg = LOAD_SP_WITH_OFFSET(ir, -2);
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uop_MEM_STORE_REG(ir, IREG_SS_base, sp_reg, src_reg);
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SUB_SP(ir, 2);
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return op_pc+1;
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}
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return 0;
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}
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uint32_t ropFF_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
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{
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x86seg *target_seg = NULL;
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int src_reg, sp_reg;
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if ((fetchdat & 0x38) != 0x00 && (fetchdat & 0x38) != 0x08 && (fetchdat & 0x38) != 0x10 && (fetchdat & 0x38) != 0x20 && (fetchdat & 0x38) != 0x28 && (fetchdat & 0x38) != 0x30)
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return 0;
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codegen_mark_code_present(block, cs+op_pc, 1);
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if ((fetchdat & 0xc0) == 0xc0)
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{
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if ((fetchdat & 0x38) == 0x28)
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return 0;
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src_reg = IREG_32(fetchdat & 7);
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}
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else
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{
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uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
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target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
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if (!(fetchdat & 0x30)) /*INC/DEC*/
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codegen_check_seg_write(block, ir, target_seg);
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else
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codegen_check_seg_read(block, ir, target_seg);
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uop_MEM_LOAD_REG(ir, IREG_temp0, ireg_seg_base(target_seg), IREG_eaaddr);
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src_reg = IREG_temp0;
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}
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switch (fetchdat & 0x38)
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{
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case 0x00: /*INC*/
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rebuild_c(ir);
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codegen_flags_changed = 1;
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if ((fetchdat & 0xc0) == 0xc0)
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|
{
|
|
uop_MOV(ir, IREG_flags_op1, src_reg);
|
|
uop_ADD_IMM(ir, src_reg, src_reg, 1);
|
|
uop_MOV(ir, IREG_flags_res, src_reg);
|
|
uop_MOV_IMM(ir, IREG_flags_op2, 1);
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_INC32);
|
|
}
|
|
else
|
|
{
|
|
uop_ADD_IMM(ir, IREG_temp1, src_reg, 1);
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1);
|
|
uop_MOV(ir, IREG_flags_op1, src_reg);
|
|
uop_MOV(ir, IREG_flags_res, IREG_temp1);
|
|
uop_MOV_IMM(ir, IREG_flags_op2, 1);
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_INC32);
|
|
}
|
|
return op_pc+1;
|
|
|
|
case 0x08: /*DEC*/
|
|
rebuild_c(ir);
|
|
codegen_flags_changed = 1;
|
|
|
|
if ((fetchdat & 0xc0) == 0xc0)
|
|
{
|
|
uop_MOV(ir, IREG_flags_op1, src_reg);
|
|
uop_SUB_IMM(ir, src_reg, src_reg, 1);
|
|
uop_MOV(ir, IREG_flags_res, src_reg);
|
|
uop_MOV_IMM(ir, IREG_flags_op2, 1);
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_DEC32);
|
|
}
|
|
else
|
|
{
|
|
uop_SUB_IMM(ir, IREG_temp1, src_reg, 1);
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1);
|
|
uop_MOV(ir, IREG_flags_op1, src_reg);
|
|
uop_MOV(ir, IREG_flags_res, IREG_temp1);
|
|
uop_MOV_IMM(ir, IREG_flags_op2, 1);
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_DEC32);
|
|
}
|
|
return op_pc+1;
|
|
|
|
case 0x10: /*CALL*/
|
|
if ((fetchdat & 0xc0) == 0xc0)
|
|
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
|
|
sp_reg = LOAD_SP_WITH_OFFSET(ir, -4);
|
|
uop_MEM_STORE_IMM_32(ir, IREG_SS_base, sp_reg, op_pc + 1);
|
|
SUB_SP(ir, 4);
|
|
uop_MOV(ir, IREG_pc, src_reg);
|
|
return -1;
|
|
|
|
case 0x20: /*JMP*/
|
|
uop_MOV(ir, IREG_pc, src_reg);
|
|
return -1;
|
|
|
|
case 0x28: /*JMP far*/
|
|
uop_MEM_LOAD_REG_OFFSET(ir, IREG_temp1_W, ireg_seg_base(target_seg), IREG_eaaddr, 4);
|
|
uop_LOAD_FUNC_ARG_REG(ir, 0, IREG_temp1_W);
|
|
uop_LOAD_FUNC_ARG_IMM(ir, 1, cpu_state.oldpc);
|
|
uop_CALL_FUNC(ir, loadcsjmp);
|
|
uop_MOV(ir, IREG_pc, src_reg);
|
|
return -1;
|
|
|
|
case 0x30: /*PUSH*/
|
|
if ((fetchdat & 0xc0) == 0xc0)
|
|
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
|
|
sp_reg = LOAD_SP_WITH_OFFSET(ir, -4);
|
|
uop_MEM_STORE_REG(ir, IREG_SS_base, sp_reg, src_reg);
|
|
SUB_SP(ir, 4);
|
|
return op_pc+1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
uint32_t ropNOP(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
|
|
{
|
|
return op_pc;
|
|
}
|
|
|
|
uint32_t ropCBW(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
|
|
{
|
|
uop_MOVSX(ir, IREG_AX, IREG_AL);
|
|
|
|
return op_pc;
|
|
}
|
|
uint32_t ropCDQ(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
|
|
{
|
|
uop_SAR_IMM(ir, IREG_EDX, IREG_EAX, 31);
|
|
|
|
return op_pc;
|
|
}
|
|
uint32_t ropCWD(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
|
|
{
|
|
uop_SAR_IMM(ir, IREG_DX, IREG_AX, 15);
|
|
|
|
return op_pc;
|
|
}
|
|
uint32_t ropCWDE(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
|
|
{
|
|
uop_MOVSX(ir, IREG_EAX, IREG_AX);
|
|
|
|
return op_pc;
|
|
}
|
|
|
|
#define ropLxS(name, seg) \
|
|
uint32_t rop ## name ## _16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
|
|
{ \
|
|
x86seg *target_seg = NULL; \
|
|
int dest_reg = (fetchdat >> 3) & 7; \
|
|
\
|
|
if ((fetchdat & 0xc0) == 0xc0) \
|
|
return 0; \
|
|
\
|
|
codegen_mark_code_present(block, cs+op_pc, 1); \
|
|
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
|
|
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
|
|
codegen_check_seg_read(block, ir, target_seg); \
|
|
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr); \
|
|
uop_MEM_LOAD_REG_OFFSET(ir, IREG_temp1_W, ireg_seg_base(target_seg), IREG_eaaddr, 2); \
|
|
uop_LOAD_SEG(ir, seg, IREG_temp1_W); \
|
|
uop_MOV(ir, IREG_16(dest_reg), IREG_temp0_W); \
|
|
\
|
|
if (seg == &cpu_state.seg_ss) \
|
|
CPU_BLOCK_END(); \
|
|
\
|
|
return op_pc + 1; \
|
|
} \
|
|
uint32_t rop ## name ## _32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
|
|
{ \
|
|
x86seg *target_seg = NULL; \
|
|
int dest_reg = (fetchdat >> 3) & 7; \
|
|
\
|
|
if ((fetchdat & 0xc0) == 0xc0) \
|
|
return 0; \
|
|
\
|
|
codegen_mark_code_present(block, cs+op_pc, 1); \
|
|
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
|
|
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
|
|
codegen_check_seg_read(block, ir, target_seg); \
|
|
uop_MEM_LOAD_REG(ir, IREG_temp0, ireg_seg_base(target_seg), IREG_eaaddr); \
|
|
uop_MEM_LOAD_REG_OFFSET(ir, IREG_temp1_W, ireg_seg_base(target_seg), IREG_eaaddr, 4); \
|
|
uop_LOAD_SEG(ir, seg, IREG_temp1_W); \
|
|
uop_MOV(ir, IREG_32(dest_reg), IREG_temp0); \
|
|
\
|
|
if (seg == &cpu_state.seg_ss) \
|
|
CPU_BLOCK_END(); \
|
|
\
|
|
return op_pc + 1; \
|
|
}
|
|
|
|
ropLxS(LDS, &cpu_state.seg_ds)
|
|
ropLxS(LES, &cpu_state.seg_es)
|
|
ropLxS(LFS, &cpu_state.seg_fs)
|
|
ropLxS(LGS, &cpu_state.seg_gs)
|
|
ropLxS(LSS, &cpu_state.seg_ss)
|
|
|
|
uint32_t ropCLC(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
|
|
{
|
|
uop_CALL_FUNC(ir, flags_rebuild);
|
|
uop_AND_IMM(ir, IREG_flags, IREG_flags, ~C_FLAG);
|
|
return op_pc;
|
|
}
|
|
uint32_t ropCMC(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
|
|
{
|
|
uop_CALL_FUNC(ir, flags_rebuild);
|
|
uop_XOR_IMM(ir, IREG_flags, IREG_flags, C_FLAG);
|
|
return op_pc;
|
|
}
|
|
uint32_t ropSTC(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
|
|
{
|
|
uop_CALL_FUNC(ir, flags_rebuild);
|
|
uop_OR_IMM(ir, IREG_flags, IREG_flags, C_FLAG);
|
|
return op_pc;
|
|
}
|
|
|
|
uint32_t ropCLD(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
|
|
{
|
|
uop_AND_IMM(ir, IREG_flags, IREG_flags, ~D_FLAG);
|
|
return op_pc;
|
|
}
|
|
uint32_t ropSTD(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
|
|
{
|
|
uop_OR_IMM(ir, IREG_flags, IREG_flags, D_FLAG);
|
|
return op_pc;
|
|
}
|
|
|
|
uint32_t ropCLI(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
|
|
{
|
|
if (!IOPLp && (cr4 & (CR4_VME | CR4_PVI)))
|
|
return 0;
|
|
|
|
uop_AND_IMM(ir, IREG_flags, IREG_flags, ~I_FLAG);
|
|
return op_pc;
|
|
}
|
|
uint32_t ropSTI(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
|
|
{
|
|
if (!IOPLp && (cr4 & (CR4_VME | CR4_PVI)))
|
|
return 0;
|
|
|
|
uop_OR_IMM(ir, IREG_flags, IREG_flags, I_FLAG);
|
|
return op_pc;
|
|
}
|