bc4f98d814
- Changed LaserXT/3 processor to 8086. - Changed LaserXT/3's minimum memory size to 512KB and granularity to 128KB. - Changed EMS size granularity to 256KB on Laser Turbo XT and 512KB on LaserXT/3. Base memory size is calculated automatically. - The mem_set_mem_state() function call for above of 1MB is called only when the memory size is more than 1024KB. Patch from Greatpsycho.
115 lines
4.4 KiB
C
115 lines
4.4 KiB
C
/*This is the chipset used in the LaserXT series model*/
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#include "ibm.h"
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#include "io.h"
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#include "mem.h"
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static int laserxt_emspage[4];
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static int laserxt_emscontrol[4];
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static mem_mapping_t laserxt_ems_mapping[4];
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static int laserxt_ems_baseaddr_index = 0;
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static uint32_t get_laserxt_ems_addr(uint32_t addr)
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{
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if (laserxt_emspage[(addr >> 14) & 3] & 0x80)
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{
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addr = (romset == ROM_LTXT ? 0x70000 + (((mem_size + 64) & 255) << 10) : 0x30000 + (((mem_size + 320) & 511) << 10)) + ((laserxt_emspage[(addr >> 14) & 3] & 0x0F) << 14) + ((laserxt_emspage[(addr >> 14) & 3] & 0x40) << 12) + (addr & 0x3FFF);
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}
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return addr;
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}
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static void laserxt_write(uint16_t port, uint8_t val, void *priv)
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{
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int i;
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uint32_t paddr, vaddr;
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switch (port)
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{
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case 0x0208: case 0x4208: case 0x8208: case 0xC208:
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laserxt_emspage[port >> 14] = val;
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paddr = 0xC0000 + (port & 0xC000) + (((laserxt_ems_baseaddr_index + (4 - (port >> 14))) & 0x0C) << 14);
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if (val & 0x80)
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{
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mem_mapping_enable(&laserxt_ems_mapping[port >> 14]);
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vaddr = get_laserxt_ems_addr(paddr);
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mem_mapping_set_exec(&laserxt_ems_mapping[port >> 14], ram + vaddr);
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}
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else
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{
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mem_mapping_disable(&laserxt_ems_mapping[port >> 14]);
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}
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flushmmucache();
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break;
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case 0x0209: case 0x4209: case 0x8209: case 0xC209:
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laserxt_emscontrol[port >> 14] = val;
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laserxt_ems_baseaddr_index = 0;
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for (i = 0; i < 4; i++)
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laserxt_ems_baseaddr_index |= (laserxt_emscontrol[i] & 0x80) >> (7 - i);
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mem_mapping_set_addr(&laserxt_ems_mapping[0], 0xC0000 + (((laserxt_ems_baseaddr_index + 4) & 0x0C) << 14), 0x4000);
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mem_mapping_set_addr(&laserxt_ems_mapping[1], 0xC4000 + (((laserxt_ems_baseaddr_index + 3) & 0x0C) << 14), 0x4000);
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mem_mapping_set_addr(&laserxt_ems_mapping[2], 0xC8000 + (((laserxt_ems_baseaddr_index + 2) & 0x0C) << 14), 0x4000);
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mem_mapping_set_addr(&laserxt_ems_mapping[3], 0xCC000 + (((laserxt_ems_baseaddr_index + 1) & 0x0C) << 14), 0x4000);
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flushmmucache();
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break;
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}
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}
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static uint8_t laserxt_read(uint16_t port, void *priv)
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{
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switch (port)
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{
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case 0x0208: case 0x4208: case 0x8208: case 0xC208:
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return laserxt_emspage[port >> 14];
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case 0x0209: case 0x4209: case 0x8209: case 0xC209:
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return laserxt_emscontrol[port >> 14];
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}
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return 0xff;
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}
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static void mem_write_laserxtems(uint32_t addr, uint8_t val, void *priv)
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{
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addr = get_laserxt_ems_addr(addr);
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if (addr < (mem_size << 10))
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ram[addr] = val;
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}
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static uint8_t mem_read_laserxtems(uint32_t addr, void *priv)
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{
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uint8_t val = 0xFF;
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addr = get_laserxt_ems_addr(addr);
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if (addr < (mem_size << 10))
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val = ram[addr];
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return val;
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}
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void laserxt_init()
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{
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int i;
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if (mem_size > 640)
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{
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io_sethandler(0x0208, 0x0002, laserxt_read, NULL, NULL, laserxt_write, NULL, NULL, NULL);
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io_sethandler(0x4208, 0x0002, laserxt_read, NULL, NULL, laserxt_write, NULL, NULL, NULL);
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io_sethandler(0x8208, 0x0002, laserxt_read, NULL, NULL, laserxt_write, NULL, NULL, NULL);
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io_sethandler(0xc208, 0x0002, laserxt_read, NULL, NULL, laserxt_write, NULL, NULL, NULL);
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mem_mapping_set_addr(&ram_low_mapping, 0, romset == ROM_LTXT ? 0x70000 + (((mem_size + 64) & 255) << 10) : 0x30000 + (((mem_size + 320) & 511) << 10));
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}
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for (i = 0; i < 4; i++)
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{
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laserxt_emspage[i] = 0x7F;
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laserxt_emscontrol[i] = (i == 3) ? 0x00 : 0x80;
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mem_mapping_add(&laserxt_ems_mapping[i], 0xE0000 + (i << 14), 0x4000, mem_read_laserxtems, NULL, NULL, mem_write_laserxtems, NULL, NULL, ram + 0xA0000 + (i << 14), 0, NULL);
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mem_mapping_disable(&laserxt_ems_mapping[i]);
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}
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mem_set_mem_state(0x0c0000, 0x40000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
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}
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