99ca11d148
This includes preliminary emulation of the VIA MVP3 northbridge, VT82C586B 'PIPC' southbridge, and Winbond W83877TF SuperIO chip.
219 lines
8.1 KiB
C
219 lines
8.1 KiB
C
#include <string.h>
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#include "ibm.h"
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#include "io.h"
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#include "mem.h"
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#include "pci.h"
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#include "mvp3.h"
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static struct
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{
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uint8_t host_bridge_regs[256];
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uint8_t pci_bridge_regs[256];
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} mvp3;
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static void mvp3_map(uint32_t addr, uint32_t size, int state)
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{
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pclog("mvp3_map: addr=%08x size=%08x state=%i\n", addr, size, state);
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switch (state & 3)
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{
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case 0:
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mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
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break;
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case 1:
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mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
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break;
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case 2:
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mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
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break;
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case 3:
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mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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break;
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}
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flushmmucache_nopc();
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}
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static uint8_t mvp3_read(int func, int addr, void *priv)
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{
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switch (func)
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{
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case 0:
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return mvp3.host_bridge_regs[addr];
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case 1:
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return mvp3.pci_bridge_regs[addr];
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default:
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return 0xff;
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}
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}
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static void mvp3_host_bridge_write(int addr, uint8_t val)
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{
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/*Read-only addresses*/
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if ((addr < 4) || (addr >= 5 && addr < 7)
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|| (addr >= 8 && addr < 0xd)
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|| (addr >= 0xe && addr < 0x12)
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|| (addr >= 0x14 && addr < 0x50)
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|| (addr >= 0x79 && addr < 0x7e)
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|| (addr >= 0x85 && addr < 0x88)
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|| (addr >= 0x8c && addr < 0xa8)
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|| (addr >= 0xad && addr < 0xfd))
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return;
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switch (addr)
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{
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case 0x04: /*Command*/
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mvp3.host_bridge_regs[0x04] = (mvp3.host_bridge_regs[0x04] & ~0x40) | (val & 0x40);
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break;
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case 0x07: /*Status*/
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mvp3.host_bridge_regs[0x07] &= ~(val & 0xb0);
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break;
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case 0x12: /*Graphics Aperture Base*/
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mvp3.host_bridge_regs[0x12] = (val & 0xf0);
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break;
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case 0x13: /*Graphics Aperture Base*/
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mvp3.host_bridge_regs[0x13] = val;
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break;
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case 0x61: /*Shadow RAM Control 1*/
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if ((mvp3.host_bridge_regs[0x61] ^ val) & 0x03)
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mvp3_map(0xc0000, 0x04000, val & 0x03);
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if ((mvp3.host_bridge_regs[0x61] ^ val) & 0x0c)
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mvp3_map(0xc4000, 0x04000, (val & 0x0c) >> 2);
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if ((mvp3.host_bridge_regs[0x61] ^ val) & 0x30)
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mvp3_map(0xc8000, 0x04000, (val & 0x30) >> 4);
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if ((mvp3.host_bridge_regs[0x61] ^ val) & 0xc0)
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mvp3_map(0xcc000, 0x04000, (val & 0xc0) >> 6);
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mvp3.host_bridge_regs[0x61] = val;
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return;
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case 0x62: /*Shadow RAM Control 2*/
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if ((mvp3.host_bridge_regs[0x62] ^ val) & 0x03)
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mvp3_map(0xd0000, 0x04000, val & 0x03);
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if ((mvp3.host_bridge_regs[0x62] ^ val) & 0x0c)
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mvp3_map(0xd4000, 0x04000, (val & 0x0c) >> 2);
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if ((mvp3.host_bridge_regs[0x62] ^ val) & 0x30)
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mvp3_map(0xd8000, 0x04000, (val & 0x30) >> 4);
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if ((mvp3.host_bridge_regs[0x62] ^ val) & 0xc0)
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mvp3_map(0xdc000, 0x04000, (val & 0xc0) >> 6);
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mvp3.host_bridge_regs[0x62] = val;
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return;
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case 0x63: /*Shadow RAM Control 3*/
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if ((mvp3.host_bridge_regs[0x63] ^ val) & 0x30)
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mvp3_map(0xf0000, 0x10000, (val & 0x30) >> 4);
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if ((mvp3.host_bridge_regs[0x63] ^ val) & 0xc0)
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mvp3_map(0xe0000, 0x10000, (val & 0xc0) >> 6);
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mvp3.host_bridge_regs[0x63] = val;
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// if (val == 0xb0)
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// output = 3;
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return;
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default:
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mvp3.host_bridge_regs[addr] = val;
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break;
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}
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}
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static void mvp3_pci_bridge_write(int addr, uint8_t val)
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{
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/*Read-only addresses*/
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if ((addr < 4) || (addr >= 5 && addr < 7)
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|| (addr >= 8 && addr < 0x18)
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|| (addr == 0x1b)
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|| (addr >= 0x1e && addr < 0x20)
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|| (addr >= 0x28 && addr < 0x3e)
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|| (addr >= 0x43))
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return;
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switch (addr)
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{
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case 0x04: /*Command*/
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mvp3.pci_bridge_regs[0x04] = (mvp3.pci_bridge_regs[0x04] & ~0x47) | (val & 0x47);
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break;
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case 0x07: /*Status*/
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mvp3.pci_bridge_regs[0x07] &= ~(val & 0x30);
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break;
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case 0x20: /*Memory Base*/
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mvp3.pci_bridge_regs[0x20] = val & 0xf0;
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break;
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case 0x22: /*Memory Limit*/
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mvp3.pci_bridge_regs[0x22] = val & 0xf0;
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break;
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case 0x24: /*Prefetchable Memory Base*/
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mvp3.pci_bridge_regs[0x24] = val & 0xf0;
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break;
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case 0x26: /*Prefetchable Memory Limit*/
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mvp3.pci_bridge_regs[0x26] = val & 0xf0;
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break;
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default:
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mvp3.pci_bridge_regs[addr] = val;
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break;
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}
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}
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static void mvp3_write(int func, int addr, uint8_t val, void *priv)
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{
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switch (func)
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{
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case 0:
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mvp3_host_bridge_write(addr, val);
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break;
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case 1:
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mvp3_pci_bridge_write(addr, val);
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break;
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}
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}
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void mvp3_init()
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{
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pci_add_specific(0, mvp3_read, mvp3_write, NULL);
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memset(&mvp3, 0, sizeof(mvp3));
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mvp3.host_bridge_regs[0x00] = 0x06; mvp3.host_bridge_regs[0x01] = 0x11; /*VIA*/
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mvp3.host_bridge_regs[0x02] = 0x98; mvp3.host_bridge_regs[0x03] = 0x05; /*VT82C598MVP*/
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mvp3.host_bridge_regs[0x04] = 0x06; mvp3.host_bridge_regs[0x05] = 0x00;
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mvp3.host_bridge_regs[0x06] = 0x90; mvp3.host_bridge_regs[0x07] = 0x02;
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mvp3.host_bridge_regs[0x0b] = 0x06;
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mvp3.host_bridge_regs[0x10] = 0x08;
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mvp3.host_bridge_regs[0x34] = 0xa0;
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mvp3.host_bridge_regs[0x5a] = 0x01;
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mvp3.host_bridge_regs[0x5b] = 0x01;
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mvp3.host_bridge_regs[0x5c] = 0x01;
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mvp3.host_bridge_regs[0x5d] = 0x01;
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mvp3.host_bridge_regs[0x5e] = 0x01;
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mvp3.host_bridge_regs[0x5f] = 0x01;
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mvp3.host_bridge_regs[0x64] = 0xec;
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mvp3.host_bridge_regs[0x65] = 0xec;
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mvp3.host_bridge_regs[0x66] = 0xec;
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mvp3.host_bridge_regs[0x6b] = 0x01;
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mvp3.host_bridge_regs[0xa0] = 0x02;
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mvp3.host_bridge_regs[0xa2] = 0x10;
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mvp3.host_bridge_regs[0xa4] = 0x03;
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mvp3.host_bridge_regs[0xa5] = 0x02;
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mvp3.host_bridge_regs[0xa6] = 0x00;
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mvp3.host_bridge_regs[0xa7] = 0x07;
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mvp3.pci_bridge_regs[0x00] = 0x06; mvp3.pci_bridge_regs[0x01] = 0x11; /*VIA*/
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mvp3.pci_bridge_regs[0x02] = 0x98; mvp3.pci_bridge_regs[0x03] = 0x85; /*VT82C598MVP*/
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mvp3.pci_bridge_regs[0x04] = 0x07; mvp3.pci_bridge_regs[0x05] = 0x00;
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mvp3.pci_bridge_regs[0x06] = 0x20; mvp3.pci_bridge_regs[0x07] = 0x02;
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mvp3.pci_bridge_regs[0x0a] = 0x04;
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mvp3.pci_bridge_regs[0x0b] = 0x06;
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mvp3.pci_bridge_regs[0x0e] = 0x01;
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mvp3.pci_bridge_regs[0x1c] = 0xf0;
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mvp3.pci_bridge_regs[0x20] = 0xf0;
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mvp3.pci_bridge_regs[0x21] = 0xff;
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mvp3.pci_bridge_regs[0x24] = 0xf0;
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mvp3.pci_bridge_regs[0x25] = 0xff;
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}
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