SarahW
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e64271f5bb
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Added recompiled versions of mem->reg, reg->mem and imm->mem versions of ADD, AND, CMP, OR, SUB and XOR.
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2018-07-27 22:24:34 +01:00 |
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SarahW
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f27b7f757a
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Add recompiled versions of mem->reg, reg->mem and imm->mem versions of MOV.
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2018-07-25 20:16:58 +01:00 |
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SarahW
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648aa0e3e8
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Added recompiled versions of 8 and 16 bit immediate->reg and reg->reg versions of MOV, ADD, SUB, CMP, AND, OR and XOR.
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2018-07-17 22:08:25 +01:00 |
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SarahW
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fc27be592c
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Added recompiled versions of immediate->reg and reg->reg versions of MOV, ADD, SUB, CMP, AND, OR and XOR.
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2018-07-08 16:36:11 +01:00 |
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SarahW
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ced37ac545
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Hacked in quick ARM64 UOP_AND_IMM handling of immediate 0xffff.
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2018-07-06 17:53:58 +01:00 |
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SarahW
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d666c0aeb9
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ARM64 UOP_ADD_IMM can now generate SUB instructions to better handle negative data.
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2018-07-06 17:53:11 +01:00 |
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SarahW
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94fea237b4
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Implemented effective address compilation.
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2018-06-28 22:06:42 +01:00 |
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SarahW
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ee3f9210dc
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Implemented basic register allocation.
Mainly handles 'virtual' registers at the moment (eg current and last PC values, segment override status, etc).
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2018-06-23 19:04:36 +01:00 |
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SarahW
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03fe25d818
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First stage of dynamic recompiler rewrite.
Basic IR generation calls C implementation of all instructions.
Backend generation implemented for x86, x86-64, ARM and ARM64.
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2018-06-17 20:26:15 +01:00 |
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