SarahW
|
66fba50e06
|
Add new codegen memory allocator. This allows the recompiler to allocate memory from a central pool as required. This central pool is by default 64 MB on x86, x86-64 and ARMv8, and 32 MB on ARMv7.
The current design does not allow for ARMv8 literal pools, therefore these have been removed.
|
2019-01-12 15:15:43 +00:00 |
|
SarahW
|
87191dde55
|
Added recompiled versions of FIST and FISTP.
|
2018-10-25 20:54:33 +01:00 |
|
SarahW
|
3332897886
|
Added recompiled versions of Jcc, JCXZ, LOOP, LOOPE and LOOPNE.
|
2018-08-30 22:26:33 +01:00 |
|
SarahW
|
f27b7f757a
|
Add recompiled versions of mem->reg, reg->mem and imm->mem versions of MOV.
|
2018-07-25 20:16:58 +01:00 |
|
SarahW
|
648aa0e3e8
|
Added recompiled versions of 8 and 16 bit immediate->reg and reg->reg versions of MOV, ADD, SUB, CMP, AND, OR and XOR.
|
2018-07-17 22:08:25 +01:00 |
|
SarahW
|
774f4201ee
|
Recompiler now handles instruction and cycle counting.
|
2018-07-06 17:51:22 +01:00 |
|
SarahW
|
94fea237b4
|
Implemented effective address compilation.
|
2018-06-28 22:06:42 +01:00 |
|
SarahW
|
ee3f9210dc
|
Implemented basic register allocation.
Mainly handles 'virtual' registers at the moment (eg current and last PC values, segment override status, etc).
|
2018-06-23 19:04:36 +01:00 |
|
SarahW
|
03fe25d818
|
First stage of dynamic recompiler rewrite.
Basic IR generation calls C implementation of all instructions.
Backend generation implemented for x86, x86-64, ARM and ARM64.
|
2018-06-17 20:26:15 +01:00 |
|