Retro/pcem
Watch
1
0
Fork
You've already forked pcem
 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions
1,645 commits 3 branches 0 tags 5.5 MiB
Commit graph pcem/src/codegen_reg.h
Author SHA1 Message Date
SarahW
6a09e9636c Disable a lot of dynarec sanity checks in release builds. 2020-11-14 19:33:51 +00:00
SarahW
25fe224ea9 Add dynarec optimisation for UOP_MOV_IMM, to avoid register allocation 
if the destination register won't be immediately used again.
 2020-11-14 19:33:50 +00:00
SarahW
0d7103368a Add register rename optimisation to dynarec to eliminate some redundant 
UOP_MOVs.
 2020-11-14 19:33:50 +00:00
SarahW
16a86adbf8 Force implicit dependency on previous register version when accessing a partial register. Fixes graphics issues in Windows 95 on Packard Bell PB410A using built-in HT216 video. 2019-04-28 10:04:30 +01:00
SarahW
7e099c277e Added basic loop unrolling. Blocks that end in a JMP, LOOP or conditional branch to a previous instruction in the block will be unrolled up to 10 times. 2019-03-25 19:07:51 +00:00
SarahW
ab124776a0 Rework self modifying code handling. 
Code blocks now have a varying level of granularity in the page and dirty masks.
Most blocks have 64-byte granularity, but blocks that are repeatedly modified
drop to 1-byte granularity. This reduces the maximum size of the affected block
significantly, but reduces recompilation due to data located too close to code.

If the block is still marked as dirty, then it is recompiled without any
immediate instruction parameters being baked into the recompiled code, instead
being fetched from the RAM array as needed. This severely reduces recompilation
rates on some SMC-heavy games, eg Duke Nukem 3D, System Shock, Screamer etc,
giving a major speedup.
 2019-03-16 14:53:26 +00:00
SarahW
3f2d9ecf87 Optimise out redundant uOPs, where the output register is never read. 2019-02-10 12:32:25 +00:00
SarahW
d4d6a26283 Added recompiled versions of ADC and SBC. 2019-02-06 21:07:45 +00:00
SarahW
095cf53265 Added segment limit checking to some instructions. 2019-02-03 17:48:11 +00:00
SarahW
335cea3ee1 Added recompiled versions of PUSHF and PUSHFD. 2018-11-28 15:19:21 +00:00
SarahW
e012420f90 Added recompiled versions of CLC, CLD, CLI, CMC, STC, STD and STI. 2018-11-28 09:58:50 +00:00
SarahW
c1565eb42f Fix partial register handling - removes pointless loads when writing to non-32-bit registers (eg FPU or MMX). 2018-11-27 19:43:01 +00:00
SarahW
76115568f2 Added recompiled versions of MOVD and MOVQ. 2018-11-21 17:02:20 +00:00
SarahW
f545d9d57f Rename FPU stack-based integer mirror registers, to avoid confusion with non-stack-based MMX registers. 2018-11-21 12:44:47 +00:00
SarahW
b814bcc80d Added recompiled versions of FSTCW and FSTSW. 2018-10-25 21:43:32 +01:00
SarahW
87191dde55 Added recompiled versions of FIST and FISTP. 2018-10-25 20:54:33 +01:00
SarahW
bce9ad4f3d Added recompiled versions of FFREE, FLD, FST, FSTP and FXCH. 2018-10-21 16:22:20 +01:00
SarahW
6d8af5df4a Added recompiled versions of memory variants of F[I]ADD, F[I]DIV, F[I]DIVR, F[I]MUL, F[I]SUB and F[I]SUBR. 2018-10-20 20:03:28 +01:00
SarahW
78996b3e5c Added recompiled register versions of FADD, FDIV, FDIVR, FMUL, FSUB and FSUBR. 2018-10-07 22:02:31 +01:00
SarahW
3332897886 Added recompiled versions of Jcc, JCXZ, LOOP, LOOPE and LOOPNE. 2018-08-30 22:26:33 +01:00
SarahW
872a2da788 Added recompiled versions of SHL, SHR, SAR, SHLD and SHRD. 2018-08-16 21:44:41 +01:00
SarahW
f1df9be8f6 Added recompiled versions of JMP, CALL, RET, PUSH and POP. 2018-08-05 16:24:15 +01:00
SarahW
e64271f5bb Added recompiled versions of mem->reg, reg->mem and imm->mem versions of ADD, AND, CMP, OR, SUB and XOR. 2018-07-27 22:24:34 +01:00
SarahW
cf508b050f End block when register version hits a maximum count. 2018-07-25 20:18:03 +01:00
SarahW
f27b7f757a Add recompiled versions of mem->reg, reg->mem and imm->mem versions of MOV. 2018-07-25 20:16:58 +01:00
SarahW
648aa0e3e8 Added recompiled versions of 8 and 16 bit immediate->reg and reg->reg versions of MOV, ADD, SUB, CMP, AND, OR and XOR. 2018-07-17 22:08:25 +01:00
SarahW
fc27be592c Added recompiled versions of immediate->reg and reg->reg versions of MOV, ADD, SUB, CMP, AND, OR and XOR. 2018-07-08 16:36:11 +01:00
SarahW
774f4201ee Recompiler now handles instruction and cycle counting. 2018-07-06 17:51:22 +01:00
SarahW
94fea237b4 Implemented effective address compilation. 2018-06-28 22:06:42 +01:00
SarahW
ee3f9210dc Implemented basic register allocation. 
Mainly handles 'virtual' registers at the moment (eg current and last PC values, segment override status, etc).
 2018-06-23 19:04:36 +01:00