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1,732 commits 3 branches 0 tags 5.5 MiB
Commit graph pcem/src/codegen_ir_defs.h
Author SHA1 Message Date
SarahW
25fe224ea9 Add dynarec optimisation for UOP_MOV_IMM, to avoid register allocation 
if the destination register won't be immediately used again.
 2020-11-14 19:33:50 +00:00
SarahW
12d73e8a95 Fix zero sized recompiled shifts. Fixes hang in Gunmetal. 2019-03-30 19:45:29 +00:00
SarahW
e8f39da459 Add recompiled versions of ROL and ROR. 2019-03-30 16:10:00 +00:00
SarahW
7e099c277e Added basic loop unrolling. Blocks that end in a JMP, LOOP or conditional branch to a previous instruction in the block will be unrolled up to 10 times. 2019-03-25 19:07:51 +00:00
SarahW
ab124776a0 Rework self modifying code handling. 
Code blocks now have a varying level of granularity in the page and dirty masks.
Most blocks have 64-byte granularity, but blocks that are repeatedly modified
drop to 1-byte granularity. This reduces the maximum size of the affected block
significantly, but reduces recompilation due to data located too close to code.

If the block is still marked as dirty, then it is recompiled without any
immediate instruction parameters being baked into the recompiled code, instead
being fetched from the RAM array as needed. This severely reduces recompilation
rates on some SMC-heavy games, eg Duke Nukem 3D, System Shock, Screamer etc,
giving a major speedup.
 2019-03-16 14:53:26 +00:00
SarahW
3f2d9ecf87 Optimise out redundant uOPs, where the output register is never read. 2019-02-10 12:32:25 +00:00
SarahW
095cf53265 Added segment limit checking to some instructions. 2019-02-03 17:48:11 +00:00
SarahW
e26abe7a1f Added recompiled versions of 3DNow instructions - PF2ID, PFADD, PFCMPEQ, PFCMPGE, PFCMPGT, PFMAX, PFMIN, PFMUL, PFRCP, PFRCPIT1, PFRCPIT2, PFRSQRT, PFRSQIT1, PFSUB, PFSUBR and PI2FD. 2018-12-14 21:59:03 +00:00
SarahW
356f406b22 Fix codegen pointer register reads. 2018-11-28 18:41:53 +00:00
SarahW
07035c97c8 Added recompiled versions of FABS, FCHS, FSQRT and FTST. 2018-11-26 17:00:00 +00:00
SarahW
2a19183d83 Added debug code to log execution rate of non-recompiled instructions. 2018-11-24 20:16:52 +00:00
SarahW
086422b79f Added recompiled versions of PMULLW, PMULHW and PMADDWD. 2018-11-24 12:52:08 +00:00
SarahW
77af266ab2 Added recompiled versions of PACK* and PUNPCK * 2018-11-23 18:34:30 +00:00
SarahW
a991bc3249 Added recompiled versions of PCMP* 2018-11-23 15:17:21 +00:00
SarahW
e43a2a6be0 Added recompiled versions of PSLL*, PSLR* and PSAR* with immediate shifts. 2018-11-22 18:43:36 +00:00
SarahW
35b9e0811b Added recompiled versions of PADD* and PSUB*. 2018-11-22 15:57:44 +00:00
SarahW
78c604c731 Added recompiled versions of PAND, PANDN, POR and PXOR 2018-11-21 20:51:34 +00:00
SarahW
76115568f2 Added recompiled versions of MOVD and MOVQ. 2018-11-21 17:02:20 +00:00
SarahW
0055238ade Added recompiled versions of FCOM, FCOMP, FCOMPP, FICOM, FICOM, FUCOM, FUCOMP and FUCOMPP. 2018-11-14 21:42:20 +00:00
SarahW
87191dde55 Added recompiled versions of FIST and FISTP. 2018-10-25 20:54:33 +01:00
SarahW
bce9ad4f3d Added recompiled versions of FFREE, FLD, FST, FSTP and FXCH. 2018-10-21 16:22:20 +01:00
SarahW
6d8af5df4a Added recompiled versions of memory variants of F[I]ADD, F[I]DIV, F[I]DIVR, F[I]MUL, F[I]SUB and F[I]SUBR. 2018-10-20 20:03:28 +01:00
SarahW
8a516df476 Added recompiled versions of FLD, FILD, FST and FSTP. 2018-10-17 19:47:04 +01:00
SarahW
78996b3e5c Added recompiled register versions of FADD, FDIV, FDIVR, FMUL, FSUB and FSUBR. 2018-10-07 22:02:31 +01:00
SarahW
592b07be63 Added recompiled versions of JMP indirect, JMP far, RETF, LxS, XLAT and LEAVE. 2018-09-29 17:42:44 +01:00
SarahW
1aadfd436d Added recompiled versions of CBW, CDQ, CWD, CWDE and MOVSX. 2018-09-23 21:45:12 +01:00
SarahW
3332897886 Added recompiled versions of Jcc, JCXZ, LOOP, LOOPE and LOOPNE. 2018-08-30 22:26:33 +01:00
SarahW
872a2da788 Added recompiled versions of SHL, SHR, SAR, SHLD and SHRD. 2018-08-16 21:44:41 +01:00
SarahW
f1df9be8f6 Added recompiled versions of JMP, CALL, RET, PUSH and POP. 2018-08-05 16:24:15 +01:00
SarahW
e64271f5bb Added recompiled versions of mem->reg, reg->mem and imm->mem versions of ADD, AND, CMP, OR, SUB and XOR. 2018-07-27 22:24:34 +01:00
SarahW
f27b7f757a Add recompiled versions of mem->reg, reg->mem and imm->mem versions of MOV. 2018-07-25 20:16:58 +01:00
SarahW
648aa0e3e8 Added recompiled versions of 8 and 16 bit immediate->reg and reg->reg versions of MOV, ADD, SUB, CMP, AND, OR and XOR. 2018-07-17 22:08:25 +01:00
SarahW
fc27be592c Added recompiled versions of immediate->reg and reg->reg versions of MOV, ADD, SUB, CMP, AND, OR and XOR. 2018-07-08 16:36:11 +01:00
SarahW
94fea237b4 Implemented effective address compilation. 2018-06-28 22:06:42 +01:00
SarahW
ee3f9210dc Implemented basic register allocation. 
Mainly handles 'virtual' registers at the moment (eg current and last PC values, segment override status, etc).
 2018-06-23 19:04:36 +01:00
SarahW
03fe25d818 First stage of dynamic recompiler rewrite. 
Basic IR generation calls C implementation of all instructions.
Backend generation implemented for x86, x86-64, ARM and ARM64.
 2018-06-17 20:26:15 +01:00