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1,785 commits 3 branches 0 tags 5.5 MiB
Commit graph pcem/src/codegen_reg.c
Author SHA1 Message Date
SarahW
6a09e9636c Disable a lot of dynarec sanity checks in release builds. 2020-11-14 19:33:51 +00:00
SarahW
25fe224ea9 Add dynarec optimisation for UOP_MOV_IMM, to avoid register allocation 
if the destination register won't be immediately used again.
 2020-11-14 19:33:50 +00:00
SarahW
0d7103368a Add register rename optimisation to dynarec to eliminate some redundant 
UOP_MOVs.
 2020-11-14 19:33:50 +00:00
SarahW
9b737f65b1 Fix warnings when compiling codegen_*.c 
Patch from davefiddes. Original commit message :

This fixes the following warnings:

codegen_allocator.c:
 - implict function declaration of rand() due to missing stdlib.h

codegen_backend_x86-64.c:
 - implict function declaration of malloc() due to missing stdlib.h
 - unused variables in codegen_backend_init()
 - invalid typecast in use of host_x86_CALL()

codegen_backend_x86-64-uop.c:
 - Remove unused variable declarations in codegen_CALL_FUNC_RESULT(),
   codegen_LOAD_SEG(), codegen_OR_IMM(), codegen_XOR() and codegen_XOR_IMM()
 - Move debug only variable declarations under the debug conditional define in
   codegen_CALL_FUNC_RESULT(), codegen_LOAD_SEG(), codegen_MEM_LOAD_SINGLE(),
   codegen_MEM_LOAD_DOUBLE(), codegen_MEM_STORE_SINGLE(),
   codegen_MEM_STORE_DOUBLE()

codegen_reg.c:
 - Change (int) typecasts to the correct (intptr_t) for small values stored
   in a pointer. This fixes a series of 64-bit compilation warnings.

Tests:
 - Build with no warnings on Fedora 32 with gcc 10.1
 - Boot a Win98 machine with dynamic compilation enabled
 2020-07-14 19:54:15 +01:00
SarahW
5e35e48ec7 XMM registers are not preserved across function calls, and should be flushed & discarded by the recompiler prior to calling external functions. Fixes graphics issues in some games (eg World Cup 98 title/menus). 2019-05-05 14:49:10 +01:00
SarahW
16a86adbf8 Force implicit dependency on previous register version when accessing a partial register. Fixes graphics issues in Windows 95 on Packard Bell PB410A using built-in HT216 video. 2019-04-28 10:04:30 +01:00
SarahW
7e099c277e Added basic loop unrolling. Blocks that end in a JMP, LOOP or conditional branch to a previous instruction in the block will be unrolled up to 10 times. 2019-03-25 19:07:51 +00:00
SarahW
3f2d9ecf87 Optimise out redundant uOPs, where the output register is never read. 2019-02-10 12:32:25 +00:00
SarahW
095cf53265 Added segment limit checking to some instructions. 2019-02-03 17:48:11 +00:00
SarahW
178c9d5c15 Don't write back temporary registers if they won't be read again. 2019-01-16 21:54:10 +00:00
SarahW
b26432caa8 When allocating a read register, prioritise registers that will not be used again. 2018-12-17 19:40:09 +00:00
SarahW
e8483acea5 Search through all host integer and FP registers when allocating registers. 2018-12-17 19:36:54 +00:00
SarahW
356f406b22 Fix codegen pointer register reads. 2018-11-28 18:41:53 +00:00
SarahW
335cea3ee1 Added recompiled versions of PUSHF and PUSHFD. 2018-11-28 15:19:21 +00:00
SarahW
e012420f90 Added recompiled versions of CLC, CLD, CLI, CMC, STC, STD and STI. 2018-11-28 09:58:50 +00:00
SarahW
c1565eb42f Fix partial register handling - removes pointless loads when writing to non-32-bit registers (eg FPU or MMX). 2018-11-27 19:43:01 +00:00
SarahW
76115568f2 Added recompiled versions of MOVD and MOVQ. 2018-11-21 17:02:20 +00:00
SarahW
f545d9d57f Rename FPU stack-based integer mirror registers, to avoid confusion with non-stack-based MMX registers. 2018-11-21 12:44:47 +00:00
SarahW
b814bcc80d Added recompiled versions of FSTCW and FSTSW. 2018-10-25 21:43:32 +01:00
SarahW
bce9ad4f3d Added recompiled versions of FFREE, FLD, FST, FSTP and FXCH. 2018-10-21 16:22:20 +01:00
SarahW
6d8af5df4a Added recompiled versions of memory variants of F[I]ADD, F[I]DIV, F[I]DIVR, F[I]MUL, F[I]SUB and F[I]SUBR. 2018-10-20 20:03:28 +01:00
SarahW
829c74f2d5 Don't write back unchanged registers on flush + invalidate. 2018-10-09 14:07:49 +01:00
SarahW
78996b3e5c Added recompiled register versions of FADD, FDIV, FDIVR, FMUL, FSUB and FSUBR. 2018-10-07 22:02:31 +01:00
SarahW
f1df9be8f6 Added recompiled versions of JMP, CALL, RET, PUSH and POP. 2018-08-05 16:24:15 +01:00
SarahW
e64271f5bb Added recompiled versions of mem->reg, reg->mem and imm->mem versions of ADD, AND, CMP, OR, SUB and XOR. 2018-07-27 22:24:34 +01:00
SarahW
f27b7f757a Add recompiled versions of mem->reg, reg->mem and imm->mem versions of MOV. 2018-07-25 20:16:58 +01:00
SarahW
648aa0e3e8 Added recompiled versions of 8 and 16 bit immediate->reg and reg->reg versions of MOV, ADD, SUB, CMP, AND, OR and XOR. 2018-07-17 22:08:25 +01:00
SarahW
fc27be592c Added recompiled versions of immediate->reg and reg->reg versions of MOV, ADD, SUB, CMP, AND, OR and XOR. 2018-07-08 16:36:11 +01:00
SarahW
774f4201ee Recompiler now handles instruction and cycle counting. 2018-07-06 17:51:22 +01:00
SarahW
94fea237b4 Implemented effective address compilation. 2018-06-28 22:06:42 +01:00
SarahW
ee3f9210dc Implemented basic register allocation. 
Mainly handles 'virtual' registers at the moment (eg current and last PC values, segment override status, etc).
 2018-06-23 19:04:36 +01:00