Add missing files from last commit.
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TomW
parent
9312de19ac
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f822488656
89 changed files with 18428 additions and 6383 deletions
645
src/x86_ops_arith.h
Normal file
645
src/x86_ops_arith.h
Normal file
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#define OP_ARITH(name, operation, setflags, flagops) \
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static int op ## name ## _b_rmw_a16(uint32_t fetchdat) \
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{ \
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int tempc = CF_SET(); \
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fetch_ea_16(fetchdat); \
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if (mod == 3) \
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{ \
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uint8_t dst = getr8(rm); \
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uint8_t src = getr8(reg); \
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setflags ## 8 flagops; \
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setr8(rm, operation); \
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cycles -= timing_rr; \
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} \
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else \
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{ \
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uint8_t dst = geteab(); if (abrt) return 0; \
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uint8_t src = getr8(reg); \
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seteab(operation); if (abrt) return 0; \
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setflags ## 8 flagops; \
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cycles -= timing_mr; \
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} \
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return 0; \
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} \
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static int op ## name ## _b_rmw_a32(uint32_t fetchdat) \
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{ \
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int tempc = CF_SET(); \
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fetch_ea_32(fetchdat); \
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if (mod == 3) \
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{ \
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uint8_t dst = getr8(rm); \
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uint8_t src = getr8(reg); \
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setflags ## 8 flagops; \
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setr8(rm, operation); \
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cycles -= timing_rr; \
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} \
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else \
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{ \
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uint8_t dst = geteab(); if (abrt) return 0; \
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uint8_t src = getr8(reg); \
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seteab(operation); if (abrt) return 0; \
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setflags ## 8 flagops; \
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cycles -= timing_mr; \
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} \
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return 0; \
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} \
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\
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static int op ## name ## _w_rmw_a16(uint32_t fetchdat) \
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{ \
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int tempc = CF_SET(); \
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fetch_ea_16(fetchdat); \
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if (mod == 3) \
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{ \
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uint16_t dst = regs[rm].w; \
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uint16_t src = regs[reg].w; \
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setflags ## 16 flagops; \
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regs[rm].w = operation; \
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cycles -= timing_rr; \
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} \
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else \
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{ \
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uint16_t dst = geteaw(); if (abrt) return 0; \
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uint16_t src = regs[reg].w; \
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seteaw(operation); if (abrt) return 0; \
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setflags ## 16 flagops; \
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cycles -= timing_mr; \
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} \
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return 0; \
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} \
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static int op ## name ## _w_rmw_a32(uint32_t fetchdat) \
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{ \
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int tempc = CF_SET(); \
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fetch_ea_32(fetchdat); \
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if (mod == 3) \
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{ \
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uint16_t dst = regs[rm].w; \
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uint16_t src = regs[reg].w; \
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setflags ## 16 flagops; \
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regs[rm].w = operation; \
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cycles -= timing_rr; \
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} \
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else \
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{ \
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uint16_t dst = geteaw(); if (abrt) return 0; \
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uint16_t src = regs[reg].w; \
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seteaw(operation); if (abrt) return 0; \
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setflags ## 16 flagops; \
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cycles -= timing_mr; \
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} \
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return 0; \
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} \
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\
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static int op ## name ## _l_rmw_a16(uint32_t fetchdat) \
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{ \
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int tempc = CF_SET(); \
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fetch_ea_16(fetchdat); \
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if (mod == 3) \
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{ \
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uint32_t dst = regs[rm].l; \
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uint32_t src = regs[reg].l; \
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setflags ## 32 flagops; \
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regs[rm].l = operation; \
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cycles -= timing_rr; \
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} \
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else \
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{ \
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uint32_t dst = geteal(); if (abrt) return 0; \
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uint32_t src = regs[reg].l; \
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seteal(operation); if (abrt) return 0; \
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setflags ## 32 flagops; \
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cycles -= timing_mrl; \
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} \
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return 0; \
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} \
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static int op ## name ## _l_rmw_a32(uint32_t fetchdat) \
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{ \
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int tempc = CF_SET(); \
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fetch_ea_32(fetchdat); \
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if (mod == 3) \
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{ \
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uint32_t dst = regs[rm].l; \
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uint32_t src = regs[reg].l; \
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setflags ## 32 flagops; \
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regs[rm].l = operation; \
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cycles -= timing_rr; \
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} \
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else \
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{ \
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uint32_t dst = geteal(); if (abrt) return 0; \
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uint32_t src = regs[reg].l; \
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seteal(operation); if (abrt) return 0; \
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setflags ## 32 flagops; \
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cycles -= timing_mrl; \
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} \
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return 0; \
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} \
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\
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static int op ## name ## _b_rm_a16(uint32_t fetchdat) \
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{ \
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int tempc = CF_SET(); \
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uint8_t dst, src; \
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fetch_ea_16(fetchdat); \
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dst = getr8(reg); \
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src = geteab(); if (abrt) return 0; \
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setflags ## 8 flagops; \
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setr8(reg, operation); \
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cycles -= (mod == 3) ? timing_rr : timing_rm; \
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return 0; \
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} \
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static int op ## name ## _b_rm_a32(uint32_t fetchdat) \
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{ \
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int tempc = CF_SET(); \
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uint8_t dst, src; \
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fetch_ea_32(fetchdat); \
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dst = getr8(reg); \
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src = geteab(); if (abrt) return 0; \
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setflags ## 8 flagops; \
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setr8(reg, operation); \
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cycles -= (mod == 3) ? timing_rr : timing_rm; \
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return 0; \
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} \
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\
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static int op ## name ## _w_rm_a16(uint32_t fetchdat) \
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{ \
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int tempc = CF_SET(); \
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uint16_t dst, src; \
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fetch_ea_16(fetchdat); \
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dst = regs[reg].w; \
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src = geteaw(); if (abrt) return 0; \
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setflags ## 16 flagops; \
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regs[reg].w = operation; \
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cycles -= (mod == 3) ? timing_rr : timing_rm; \
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return 0; \
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} \
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static int op ## name ## _w_rm_a32(uint32_t fetchdat) \
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{ \
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int tempc = CF_SET(); \
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uint16_t dst, src; \
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fetch_ea_32(fetchdat); \
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dst = regs[reg].w; \
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src = geteaw(); if (abrt) return 0; \
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setflags ## 16 flagops; \
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regs[reg].w = operation; \
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cycles -= (mod == 3) ? timing_rr : timing_rm; \
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return 0; \
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} \
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\
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static int op ## name ## _l_rm_a16(uint32_t fetchdat) \
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{ \
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int tempc = CF_SET(); \
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uint32_t dst, src; \
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fetch_ea_16(fetchdat); \
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dst = regs[reg].l; \
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src = geteal(); if (abrt) return 0; \
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setflags ## 32 flagops; \
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regs[reg].l = operation; \
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cycles -= (mod == 3) ? timing_rr : timing_rml; \
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return 0; \
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} \
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static int op ## name ## _l_rm_a32(uint32_t fetchdat) \
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{ \
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int tempc = CF_SET(); \
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uint32_t dst, src; \
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fetch_ea_32(fetchdat); \
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dst = regs[reg].l; \
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src = geteal(); if (abrt) return 0; \
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setflags ## 32 flagops; \
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regs[reg].l = operation; \
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cycles -= (mod == 3) ? timing_rr : timing_rml; \
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return 0; \
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} \
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\
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static int op ## name ## _AL_imm(uint32_t fetchdat) \
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{ \
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int tempc = CF_SET(); \
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uint8_t dst = AL; \
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uint8_t src = getbytef(); \
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setflags ## 8 flagops; \
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AL = operation; \
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cycles -= timing_rr; \
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return 0; \
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} \
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\
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static int op ## name ## _AX_imm(uint32_t fetchdat) \
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{ \
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int tempc = CF_SET(); \
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uint16_t dst = AX; \
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uint16_t src = getwordf(); \
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setflags ## 16 flagops; \
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AX = operation; \
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cycles -= timing_rr; \
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return 0; \
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} \
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\
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static int op ## name ## _EAX_imm(uint32_t fetchdat) \
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{ \
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int tempc = CF_SET(); \
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uint32_t dst = EAX; \
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uint32_t src = getlong(); \
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setflags ## 32 flagops; \
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EAX = operation; \
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cycles -= timing_rr; \
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return 0; \
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}
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OP_ARITH(ADD, dst + src, setadd, (dst, src))
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OP_ARITH(ADC, dst + src + tempc, setadc, (dst, src))
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OP_ARITH(SUB, dst - src, setsub, (dst, src))
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OP_ARITH(SBB, dst - (src + tempc), setsbc, (dst, src))
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OP_ARITH(OR, dst | src, setznp, (dst | src))
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OP_ARITH(AND, dst & src, setznp, (dst & src))
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OP_ARITH(XOR, dst ^ src, setznp, (dst ^ src))
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static int opCMP_b_rmw_a16(uint32_t fetchdat)
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{
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uint8_t dst;
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fetch_ea_16(fetchdat);
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dst = geteab(); if (abrt) return 0;
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setsub8(dst, getr8(reg));
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if (is486) cycles -= ((mod == 3) ? 1 : 2);
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else cycles -= ((mod == 3) ? 2 : 5);
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return 0;
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}
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static int opCMP_b_rmw_a32(uint32_t fetchdat)
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{
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uint8_t dst;
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fetch_ea_32(fetchdat);
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dst = geteab(); if (abrt) return 0;
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setsub8(dst, getr8(reg));
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if (is486) cycles -= ((mod == 3) ? 1 : 2);
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else cycles -= ((mod == 3) ? 2 : 5);
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return 0;
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}
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static int opCMP_w_rmw_a16(uint32_t fetchdat)
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{
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uint16_t dst;
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fetch_ea_16(fetchdat);
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dst = geteaw(); if (abrt) return 0;
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setsub16(dst, regs[reg].w);
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if (is486) cycles -= ((mod == 3) ? 1 : 2);
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else cycles -= ((mod == 3) ? 2 : 5);
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return 0;
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}
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static int opCMP_w_rmw_a32(uint32_t fetchdat)
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{
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uint16_t dst;
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fetch_ea_32(fetchdat);
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dst = geteaw(); if (abrt) return 0;
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setsub16(dst, regs[reg].w);
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if (is486) cycles -= ((mod == 3) ? 1 : 2);
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else cycles -= ((mod == 3) ? 2 : 5);
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return 0;
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}
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static int opCMP_l_rmw_a16(uint32_t fetchdat)
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{
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uint32_t dst;
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fetch_ea_16(fetchdat);
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dst = geteal(); if (abrt) return 0;
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setsub32(dst, regs[reg].l);
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if (is486) cycles -= ((mod == 3) ? 1 : 2);
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else cycles -= ((mod == 3) ? 2 : 5);
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return 0;
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}
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static int opCMP_l_rmw_a32(uint32_t fetchdat)
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{
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uint32_t dst;
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fetch_ea_32(fetchdat);
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dst = geteal(); if (abrt) return 0;
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setsub32(dst, regs[reg].l);
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if (is486) cycles -= ((mod == 3) ? 1 : 2);
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else cycles -= ((mod == 3) ? 2 : 5);
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return 0;
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}
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static int opCMP_b_rm_a16(uint32_t fetchdat)
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{
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uint8_t src;
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fetch_ea_16(fetchdat);
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src = geteab(); if (abrt) return 0;
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setsub8(getr8(reg), src);
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cycles -= (mod == 3) ? timing_rr : timing_rm;
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return 0;
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}
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static int opCMP_b_rm_a32(uint32_t fetchdat)
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{
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uint8_t src;
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fetch_ea_32(fetchdat);
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src = geteab(); if (abrt) return 0;
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setsub8(getr8(reg), src);
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cycles -= (mod == 3) ? timing_rr : timing_rm;
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return 0;
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}
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static int opCMP_w_rm_a16(uint32_t fetchdat)
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{
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uint16_t src;
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fetch_ea_16(fetchdat);
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src = geteaw(); if (abrt) return 0;
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setsub16(regs[reg].w, src);
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cycles -= (mod == 3) ? timing_rr : timing_rm;
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return 0;
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}
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static int opCMP_w_rm_a32(uint32_t fetchdat)
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{
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uint16_t src;
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fetch_ea_32(fetchdat);
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src = geteaw(); if (abrt) return 0;
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setsub16(regs[reg].w, src);
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cycles -= (mod == 3) ? timing_rr : timing_rm;
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return 0;
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}
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static int opCMP_l_rm_a16(uint32_t fetchdat)
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{
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uint32_t src;
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fetch_ea_16(fetchdat);
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src = geteal(); if (abrt) return 0;
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setsub32(regs[reg].l, src);
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cycles -= (mod == 3) ? timing_rr : timing_rml;
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return 0;
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}
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static int opCMP_l_rm_a32(uint32_t fetchdat)
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{
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uint32_t src;
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fetch_ea_32(fetchdat);
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src = geteal(); if (abrt) return 0;
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setsub32(regs[reg].l, src);
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cycles -= (mod == 3) ? timing_rr : timing_rml;
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return 0;
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}
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static int opCMP_AL_imm(uint32_t fetchdat)
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{
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uint8_t src = getbytef();
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setsub8(AL, src);
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cycles -= timing_rr;
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return 0;
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}
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static int opCMP_AX_imm(uint32_t fetchdat)
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{
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uint16_t src = getwordf();
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setsub16(AX, src);
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cycles -= timing_rr;
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return 0;
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}
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static int opCMP_EAX_imm(uint32_t fetchdat)
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{
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uint32_t src = getlong();
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setsub32(EAX, src);
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cycles -= timing_rr;
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return 0;
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}
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static int opTEST_b_a16(uint32_t fetchdat)
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{
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uint8_t temp, temp2;
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fetch_ea_16(fetchdat);
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temp = geteab(); if (abrt) return 0;
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temp2 = getr8(reg);
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setznp8(temp & temp2);
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if (is486) cycles -= ((mod == 3) ? 1 : 2);
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else cycles -= ((mod == 3) ? 2 : 5);
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return 0;
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}
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static int opTEST_b_a32(uint32_t fetchdat)
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{
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uint8_t temp, temp2;
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fetch_ea_32(fetchdat);
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temp = geteab(); if (abrt) return 0;
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temp2 = getr8(reg);
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setznp8(temp & temp2);
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if (is486) cycles -= ((mod == 3) ? 1 : 2);
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else cycles -= ((mod == 3) ? 2 : 5);
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return 0;
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}
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static int opTEST_w_a16(uint32_t fetchdat)
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{
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uint16_t temp, temp2;
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fetch_ea_16(fetchdat);
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temp = geteaw(); if (abrt) return 0;
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temp2 = regs[reg].w;
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setznp16(temp & temp2);
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if (is486) cycles -= ((mod == 3) ? 1 : 2);
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else cycles -= ((mod == 3) ? 2 : 5);
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return 0;
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}
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static int opTEST_w_a32(uint32_t fetchdat)
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{
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uint16_t temp, temp2;
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fetch_ea_32(fetchdat);
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temp = geteaw(); if (abrt) return 0;
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temp2 = regs[reg].w;
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setznp16(temp & temp2);
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if (is486) cycles -= ((mod == 3) ? 1 : 2);
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else cycles -= ((mod == 3) ? 2 : 5);
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return 0;
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}
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static int opTEST_l_a16(uint32_t fetchdat)
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{
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uint32_t temp, temp2;
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fetch_ea_16(fetchdat);
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temp = geteal(); if (abrt) return 0;
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temp2 = regs[reg].l;
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setznp32(temp & temp2);
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if (is486) cycles -= ((mod == 3) ? 1 : 2);
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else cycles -= ((mod == 3) ? 2 : 5);
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return 0;
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}
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static int opTEST_l_a32(uint32_t fetchdat)
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{
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uint32_t temp, temp2;
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fetch_ea_32(fetchdat);
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temp = geteal(); if (abrt) return 0;
|
||||
temp2 = regs[reg].l;
|
||||
setznp32(temp & temp2);
|
||||
if (is486) cycles -= ((mod == 3) ? 1 : 2);
|
||||
else cycles -= ((mod == 3) ? 2 : 5);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int opTEST_AL(uint32_t fetchdat)
|
||||
{
|
||||
uint8_t temp = getbytef();
|
||||
setznp8(AL & temp);
|
||||
cycles -= timing_rr;
|
||||
return 0;
|
||||
}
|
||||
static int opTEST_AX(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t temp = getwordf();
|
||||
setznp16(AX & temp);
|
||||
cycles -= timing_rr;
|
||||
return 0;
|
||||
}
|
||||
static int opTEST_EAX(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t temp = getlong(); if (abrt) return 0;
|
||||
setznp32(EAX & temp);
|
||||
cycles -= timing_rr;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
#define ARITH_MULTI(ea_width, flag_width) \
|
||||
dst = getea ## ea_width(); if (abrt) return 0; \
|
||||
switch (rmdat&0x38) \
|
||||
{ \
|
||||
case 0x00: /*ADD ea, #*/ \
|
||||
setea ## ea_width(dst + src); if (abrt) return 0; \
|
||||
setadd ## flag_width(dst, src); \
|
||||
cycles -= (mod == 3) ? timing_rr : timing_mr; \
|
||||
break; \
|
||||
case 0x08: /*OR ea, #*/ \
|
||||
dst |= src; \
|
||||
setea ## ea_width(dst); if (abrt) return 0; \
|
||||
setznp ## flag_width(dst); \
|
||||
cycles -= (mod == 3) ? timing_rr : timing_mr; \
|
||||
break; \
|
||||
case 0x10: /*ADC ea, #*/ \
|
||||
setea ## ea_width(dst + src + tempc); if (abrt) return 0; \
|
||||
setadc ## flag_width(dst, src); \
|
||||
cycles -= (mod == 3) ? timing_rr : timing_mr; \
|
||||
break; \
|
||||
case 0x18: /*SBB ea, #*/ \
|
||||
setea ## ea_width(dst - (src + tempc)); if (abrt) return 0; \
|
||||
setsbc ## flag_width(dst, src); \
|
||||
cycles -= (mod == 3) ? timing_rr : timing_mr; \
|
||||
break; \
|
||||
case 0x20: /*AND ea, #*/ \
|
||||
dst &= src; \
|
||||
setea ## ea_width(dst); if (abrt) return 0; \
|
||||
setznp ## flag_width(dst); \
|
||||
cycles -= (mod == 3) ? timing_rr : timing_mr; \
|
||||
break; \
|
||||
case 0x28: /*SUB ea, #*/ \
|
||||
setea ## ea_width(dst - src); if (abrt) return 0; \
|
||||
setsub ## flag_width(dst, src); \
|
||||
cycles -= (mod == 3) ? timing_rr : timing_mr; \
|
||||
break; \
|
||||
case 0x30: /*XOR ea, #*/ \
|
||||
dst ^= src; \
|
||||
setea ## ea_width(dst); if (abrt) return 0; \
|
||||
setznp ## flag_width(dst); \
|
||||
cycles -= (mod == 3) ? timing_rr : timing_mr; \
|
||||
break; \
|
||||
case 0x38: /*CMP ea, #*/ \
|
||||
setsub ## flag_width(dst, src); \
|
||||
if (is486) cycles -= ((mod == 3) ? 1 : 2); \
|
||||
else cycles -= ((mod == 3) ? 2 : 7); \
|
||||
break; \
|
||||
}
|
||||
|
||||
|
||||
static int op80_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint8_t src, dst;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
src = getbyte(); if (abrt) return 0;
|
||||
ARITH_MULTI(b, 8);
|
||||
|
||||
return 0;
|
||||
}
|
||||
static int op80_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint8_t src, dst;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
src = getbyte(); if (abrt) return 0;
|
||||
ARITH_MULTI(b, 8);
|
||||
|
||||
return 0;
|
||||
}
|
||||
static int op81_w_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t src, dst;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
src = getword(); if (abrt) return 0;
|
||||
ARITH_MULTI(w, 16);
|
||||
|
||||
return 0;
|
||||
}
|
||||
static int op81_w_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t src, dst;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
src = getword(); if (abrt) return 0;
|
||||
ARITH_MULTI(w, 16);
|
||||
|
||||
return 0;
|
||||
}
|
||||
static int op81_l_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t src, dst;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
src = getlong(); if (abrt) return 0;
|
||||
ARITH_MULTI(l, 32);
|
||||
|
||||
return 0;
|
||||
}
|
||||
static int op81_l_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t src, dst;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
src = getlong(); if (abrt) return 0;
|
||||
ARITH_MULTI(l, 32);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int op83_w_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t src, dst;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
src = getbyte(); if (abrt) return 0;
|
||||
if (src & 0x80) src |= 0xff00;
|
||||
ARITH_MULTI(w, 16);
|
||||
|
||||
return 0;
|
||||
}
|
||||
static int op83_w_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t src, dst;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
src = getbyte(); if (abrt) return 0;
|
||||
if (src & 0x80) src |= 0xff00;
|
||||
ARITH_MULTI(w, 16);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int op83_l_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t src, dst;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
src = getbyte(); if (abrt) return 0;
|
||||
if (src & 0x80) src |= 0xffffff00;
|
||||
ARITH_MULTI(l, 32);
|
||||
|
||||
return 0;
|
||||
}
|
||||
static int op83_l_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t src, dst;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
src = getbyte(); if (abrt) return 0;
|
||||
if (src & 0x80) src |= 0xffffff00;
|
||||
ARITH_MULTI(l, 32);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
Loading…
Reference in a new issue