From f545d9d57f681c5d6606378eef0b36935a478382 Mon Sep 17 00:00:00 2001 From: SarahW Date: Wed, 21 Nov 2018 12:44:47 +0000 Subject: [PATCH] Rename FPU stack-based integer mirror registers, to avoid confusion with non-stack-based MMX registers. --- src/codegen_ops_fpu_loadstore.c | 6 +++--- src/codegen_ops_fpu_misc.c | 12 ++++++------ src/codegen_reg.c | 16 ++++++++-------- src/codegen_reg.h | 20 ++++++++++---------- 4 files changed, 27 insertions(+), 27 deletions(-) diff --git a/src/codegen_ops_fpu_loadstore.c b/src/codegen_ops_fpu_loadstore.c index 8be00d2..04ee62a 100644 --- a/src/codegen_ops_fpu_loadstore.c +++ b/src/codegen_ops_fpu_loadstore.c @@ -141,8 +141,8 @@ uint32_t ropFILDq(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fe op_pc--; target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); codegen_check_seg_read(block, ir, target_seg); - uop_MEM_LOAD_REG(ir, IREG_MM(-1), ireg_seg_base(target_seg), IREG_eaaddr); - uop_MOV_DOUBLE_INT(ir, IREG_ST(-1), IREG_MM(-1)); + uop_MEM_LOAD_REG(ir, IREG_ST_i64(-1), ireg_seg_base(target_seg), IREG_eaaddr); + uop_MOV_DOUBLE_INT(ir, IREG_ST(-1), IREG_ST_i64(-1)); uop_MOV_IMM(ir, IREG_tag(-1), TAG_VALID | TAG_UINT64); fpu_PUSH(ir); @@ -220,7 +220,7 @@ uint32_t ropFISTPq(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t f op_pc--; target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); codegen_check_seg_write(block, ir, target_seg); - uop_MOV_INT_DOUBLE_64(ir, IREG_temp0_Q, IREG_ST(0), IREG_MM(0), IREG_tag(0)); + uop_MOV_INT_DOUBLE_64(ir, IREG_temp0_Q, IREG_ST(0), IREG_ST_i64(0), IREG_tag(0)); uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_Q); uop_MOV_IMM(ir, IREG_tag(0), TAG_EMPTY); fpu_POP(ir); diff --git a/src/codegen_ops_fpu_misc.c b/src/codegen_ops_fpu_misc.c index 2509cc7..18d6f88 100644 --- a/src/codegen_ops_fpu_misc.c +++ b/src/codegen_ops_fpu_misc.c @@ -27,7 +27,7 @@ uint32_t ropFLD(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetc uop_FP_ENTER(ir); uop_MOV(ir, IREG_ST(-1), IREG_ST(src_reg)); - uop_MOV(ir, IREG_MM(-1), IREG_MM(src_reg)); + uop_MOV(ir, IREG_ST_i64(-1), IREG_ST_i64(src_reg)); uop_MOV(ir, IREG_tag(-1), IREG_tag(src_reg)); fpu_PUSH(ir); @@ -40,7 +40,7 @@ uint32_t ropFST(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetc uop_FP_ENTER(ir); uop_MOV(ir, IREG_ST(dest_reg), IREG_ST(0)); - uop_MOV(ir, IREG_MM(dest_reg), IREG_MM(0)); + uop_MOV(ir, IREG_ST_i64(dest_reg), IREG_ST_i64(0)); uop_MOV(ir, IREG_tag(dest_reg), IREG_tag(0)); return op_pc; @@ -51,7 +51,7 @@ uint32_t ropFSTP(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fet uop_FP_ENTER(ir); uop_MOV(ir, IREG_ST(dest_reg), IREG_ST(0)); - uop_MOV(ir, IREG_MM(dest_reg), IREG_MM(0)); + uop_MOV(ir, IREG_ST_i64(dest_reg), IREG_ST_i64(0)); uop_MOV(ir, IREG_tag(dest_reg), IREG_tag(0)); fpu_POP(ir); @@ -98,13 +98,13 @@ uint32_t ropFXCH(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fet uop_FP_ENTER(ir); uop_MOV(ir, IREG_temp0_D, IREG_ST(0)); - uop_MOV(ir, IREG_temp1_Q, IREG_MM(0)); + uop_MOV(ir, IREG_temp1_Q, IREG_ST_i64(0)); uop_MOV(ir, IREG_temp2, IREG_tag(0)); uop_MOV(ir, IREG_ST(0), IREG_ST(dest_reg)); - uop_MOV(ir, IREG_MM(0), IREG_MM(dest_reg)); + uop_MOV(ir, IREG_ST_i64(0), IREG_ST_i64(dest_reg)); uop_MOV(ir, IREG_tag(0), IREG_tag(dest_reg)); uop_MOV(ir, IREG_ST(dest_reg), IREG_temp0_D); - uop_MOV(ir, IREG_MM(dest_reg), IREG_temp1_Q); + uop_MOV(ir, IREG_ST_i64(dest_reg), IREG_temp1_Q); uop_MOV(ir, IREG_tag(dest_reg), IREG_temp2); return op_pc; diff --git a/src/codegen_reg.c b/src/codegen_reg.c index 2e76874..6e51f7d 100644 --- a/src/codegen_reg.c +++ b/src/codegen_reg.c @@ -114,14 +114,14 @@ struct [IREG_tag6] = {REG_FPU_ST_BYTE, &cpu_state.tag[0], REG_INTEGER}, [IREG_tag7] = {REG_FPU_ST_BYTE, &cpu_state.tag[0], REG_INTEGER}, - [IREG_MM0] = {REG_FPU_ST_QWORD, &cpu_state.MM[0], REG_FP}, - [IREG_MM1] = {REG_FPU_ST_QWORD, &cpu_state.MM[0], REG_FP}, - [IREG_MM2] = {REG_FPU_ST_QWORD, &cpu_state.MM[0], REG_FP}, - [IREG_MM3] = {REG_FPU_ST_QWORD, &cpu_state.MM[0], REG_FP}, - [IREG_MM4] = {REG_FPU_ST_QWORD, &cpu_state.MM[0], REG_FP}, - [IREG_MM5] = {REG_FPU_ST_QWORD, &cpu_state.MM[0], REG_FP}, - [IREG_MM6] = {REG_FPU_ST_QWORD, &cpu_state.MM[0], REG_FP}, - [IREG_MM7] = {REG_FPU_ST_QWORD, &cpu_state.MM[0], REG_FP}, + [IREG_ST0_i64] = {REG_FPU_ST_QWORD, &cpu_state.MM[0], REG_FP}, + [IREG_ST1_i64] = {REG_FPU_ST_QWORD, &cpu_state.MM[0], REG_FP}, + [IREG_ST2_i64] = {REG_FPU_ST_QWORD, &cpu_state.MM[0], REG_FP}, + [IREG_ST3_i64] = {REG_FPU_ST_QWORD, &cpu_state.MM[0], REG_FP}, + [IREG_ST4_i64] = {REG_FPU_ST_QWORD, &cpu_state.MM[0], REG_FP}, + [IREG_ST5_i64] = {REG_FPU_ST_QWORD, &cpu_state.MM[0], REG_FP}, + [IREG_ST6_i64] = {REG_FPU_ST_QWORD, &cpu_state.MM[0], REG_FP}, + [IREG_ST7_i64] = {REG_FPU_ST_QWORD, &cpu_state.MM[0], REG_FP}, [IREG_NPXCx] = {REG_WORD, &cpu_state.npxc, REG_INTEGER}, [IREG_NPXSx] = {REG_WORD, &cpu_state.npxs, REG_INTEGER}, diff --git a/src/codegen_reg.h b/src/codegen_reg.h index 3bb69b2..4568382 100644 --- a/src/codegen_reg.h +++ b/src/codegen_reg.h @@ -95,14 +95,14 @@ enum IREG_tag6 = 54, IREG_tag7 = 55, - IREG_MM0 = 56, - IREG_MM1 = 57, - IREG_MM2 = 58, - IREG_MM3 = 59, - IREG_MM4 = 60, - IREG_MM5 = 61, - IREG_MM6 = 62, - IREG_MM7 = 63, + IREG_ST0_i64 = 56, + IREG_ST1_i64 = 57, + IREG_ST2_i64 = 58, + IREG_ST3_i64 = 59, + IREG_ST4_i64 = 60, + IREG_ST5_i64 = 61, + IREG_ST6_i64 = 62, + IREG_ST7_i64 = 63, IREG_NPXCx = 64, IREG_NPXSx = 65, @@ -168,8 +168,8 @@ enum #define IREG_16(reg) ((reg) + IREG_AX) #define IREG_32(reg) ((reg) + IREG_EAX) -#define IREG_ST(r) (IREG_ST0 + ((cpu_state.TOP + (r)) & 7) + IREG_SIZE_D) -#define IREG_MM(r) (IREG_MM0 + ((cpu_state.TOP + (r)) & 7) + IREG_SIZE_Q) +#define IREG_ST(r) (IREG_ST0 + ((cpu_state.TOP + (r)) & 7) + IREG_SIZE_D) +#define IREG_ST_i64(r) (IREG_ST0_i64 + ((cpu_state.TOP + (r)) & 7) + IREG_SIZE_Q) #define IREG_tag(r) (IREG_tag0 + ((cpu_state.TOP + (r)) & 7)) #define IREG_tag_B(r) (IREG_tag0 + ((cpu_state.TOP + (r)) & 7) + IREG_SIZE_B)