Added code generation for :
- FCOM/FUCOM - FSUBR/FSUBRP/FDIVR/FDIVRP - FLDCW/FSTCW - FILD/FIST/FISTP (16-bit, 32-bit and 64-bit variants) - FLD/FST/FSTP double precision - Integer and double precision variants of FADD/FSUB/FMUL/FDIV Also added 64-bit readmemq/writememq functions.
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f5a920e2e5
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f3607c2308
11 changed files with 1398 additions and 241 deletions
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@ -94,12 +94,10 @@ static int opMOVQ_q_mm_a16(uint32_t fetchdat)
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}
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else
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{
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uint32_t dst[2];
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uint64_t dst;
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dst[0] = readmeml(easeg, eaaddr);
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dst[1] = readmeml(easeg, eaaddr + 4); if (abrt) return 1;
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MM[reg].l[0] = dst[0];
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MM[reg].l[1] = dst[1];
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dst = readmemq(easeg, eaaddr); if (abrt) return 1;
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MM[reg].q = dst;
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CLOCK_CYCLES(2);
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}
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return 0;
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@ -116,12 +114,10 @@ static int opMOVQ_q_mm_a32(uint32_t fetchdat)
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}
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else
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{
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uint32_t dst[2];
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uint64_t dst;
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dst[0] = readmeml(easeg, eaaddr);
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dst[1] = readmeml(easeg, eaaddr + 4); if (abrt) return 1;
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MM[reg].l[0] = dst[0];
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MM[reg].l[1] = dst[1];
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dst = readmemq(easeg, eaaddr); if (abrt) return 1;
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MM[reg].q = dst;
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CLOCK_CYCLES(2);
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}
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return 0;
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@ -140,9 +136,7 @@ static int opMOVQ_mm_q_a16(uint32_t fetchdat)
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else
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{
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CHECK_WRITE(ea_seg, eaaddr, eaaddr + 7);
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writememl(easeg, eaaddr, MM[reg].l[0]);
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writememl(easeg, eaaddr + 4, MM[reg].l[1]); if (abrt) return 1;
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CLOCK_CYCLES(2);
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writememq(easeg, eaaddr, MM[reg].l[0]);
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}
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return 0;
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}
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@ -159,9 +153,7 @@ static int opMOVQ_mm_q_a32(uint32_t fetchdat)
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else
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{
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CHECK_WRITE(ea_seg, eaaddr, eaaddr + 7);
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writememl(easeg, eaaddr, MM[reg].l[0]);
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writememl(easeg, eaaddr + 4, MM[reg].l[1]); if (abrt) return 1;
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CLOCK_CYCLES(2);
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writememq(easeg, eaaddr, MM[reg].q);
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}
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return 0;
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}
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