Interpreter and dynamic recompiler now present in a single binary.
This commit is contained in:
TomW
parent
969d5811e5
commit
f339f00315
25 changed files with 365 additions and 1208 deletions
300
src/cpu.c
300
src/cpu.c
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@ -3,12 +3,9 @@
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#include "model.h"
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#include "io.h"
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#include "x86_ops.h"
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#ifdef DYNAREC
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#include "mem.h"
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#include "codegen.h"
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#endif
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#ifdef DYNAREC
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OpFn *x86_dynarec_opcodes;
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OpFn *x86_dynarec_opcodes_0f;
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OpFn *x86_dynarec_opcodes_d8_a16;
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@ -27,7 +24,6 @@ OpFn *x86_dynarec_opcodes_de_a16;
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OpFn *x86_dynarec_opcodes_de_a32;
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OpFn *x86_dynarec_opcodes_df_a16;
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OpFn *x86_dynarec_opcodes_df_a32;
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#endif
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OpFn *x86_opcodes;
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OpFn *x86_opcodes_0f;
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@ -66,6 +62,7 @@ int cpu_busspeed;
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int cpu_hasrdtsc;
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int cpu_hasMMX, cpu_hasMSR;
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int cpu_hasCR4;
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int cpu_use_dynarec;
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uint64_t cpu_CR4_mask;
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@ -109,228 +106,226 @@ static struct
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CPU cpus_8088[] =
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{
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/*8088 standard*/
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{"8088/4.77", CPU_8088, 0, 4772727, 1, 0, 0, 0},
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{"8088/8", CPU_8088, 1, 8000000, 1, 0, 0, 0},
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{"8088/10", CPU_8088, 2, 10000000, 1, 0, 0, 0},
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{"8088/12", CPU_8088, 3, 12000000, 1, 0, 0, 0},
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{"8088/16", CPU_8088, 4, 16000000, 1, 0, 0, 0},
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{"8088/4.77", CPU_8088, 0, 4772727, 1, 0, 0, 0, 0},
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{"8088/8", CPU_8088, 1, 8000000, 1, 0, 0, 0, 0},
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{"8088/10", CPU_8088, 2, 10000000, 1, 0, 0, 0, 0},
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{"8088/12", CPU_8088, 3, 12000000, 1, 0, 0, 0, 0},
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{"8088/16", CPU_8088, 4, 16000000, 1, 0, 0, 0, 0},
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{"", -1, 0, 0, 0, 0}
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};
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CPU cpus_pcjr[] =
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{
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/*8088 PCjr*/
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{"8088/4.77", CPU_8088, 0, 4772727, 1, 0, 0, 0},
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{"8088/4.77", CPU_8088, 0, 4772727, 1, 0, 0, 0, 0},
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{"", -1, 0, 0, 0, 0}
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};
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CPU cpus_8086[] =
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{
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/*8086 standard*/
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{"8086/7.16", CPU_8086, 1, 3579545*2, 1, 0, 0, 0},
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{"8086/8", CPU_8086, 1, 8000000, 1, 0, 0, 0},
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{"8086/9.54", CPU_8086, 1, (3579545*8)/3, 1, 0, 0, 0},
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{"8086/10", CPU_8086, 2, 10000000, 1, 0, 0, 0},
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{"8086/12", CPU_8086, 3, 12000000, 1, 0, 0, 0},
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{"8086/16", CPU_8086, 4, 16000000, 1, 0, 0, 0},
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{"8086/7.16", CPU_8086, 1, 3579545*2, 1, 0, 0, 0, 0},
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{"8086/8", CPU_8086, 1, 8000000, 1, 0, 0, 0, 0},
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{"8086/9.54", CPU_8086, 1, (3579545*8)/3, 1, 0, 0, 0, 0},
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{"8086/10", CPU_8086, 2, 10000000, 1, 0, 0, 0, 0},
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{"8086/12", CPU_8086, 3, 12000000, 1, 0, 0, 0, 0},
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{"8086/16", CPU_8086, 4, 16000000, 1, 0, 0, 0, 0},
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{"", -1, 0, 0, 0, 0}
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};
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CPU cpus_pc1512[] =
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{
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/*8086 Amstrad*/
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{"8086/8", CPU_8086, 1, 8000000, 1, 0, 0, 0},
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{"8086/8", CPU_8086, 1, 8000000, 1, 0, 0, 0, 0},
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{"", -1, 0, 0, 0, 0}
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};
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CPU cpus_286[] =
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{
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/*286*/
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{"286/6", CPU_286, 0, 6000000, 1, 0, 0, 0},
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{"286/8", CPU_286, 1, 8000000, 1, 0, 0, 0},
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{"286/10", CPU_286, 2, 10000000, 1, 0, 0, 0},
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{"286/12", CPU_286, 3, 12000000, 1, 0, 0, 0},
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{"286/16", CPU_286, 4, 16000000, 1, 0, 0, 0},
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{"286/20", CPU_286, 5, 20000000, 1, 0, 0, 0},
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{"286/25", CPU_286, 6, 25000000, 1, 0, 0, 0},
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{"286/6", CPU_286, 0, 6000000, 1, 0, 0, 0, 0},
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{"286/8", CPU_286, 1, 8000000, 1, 0, 0, 0, 0},
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{"286/10", CPU_286, 2, 10000000, 1, 0, 0, 0, 0},
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{"286/12", CPU_286, 3, 12000000, 1, 0, 0, 0, 0},
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{"286/16", CPU_286, 4, 16000000, 1, 0, 0, 0, 0},
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{"286/20", CPU_286, 5, 20000000, 1, 0, 0, 0, 0},
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{"286/25", CPU_286, 6, 25000000, 1, 0, 0, 0, 0},
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{"", -1, 0, 0, 0, 0}
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};
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CPU cpus_ibmat[] =
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{
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/*286*/
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{"286/6", CPU_286, 0, 6000000, 1, 0, 0, 0},
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{"286/8", CPU_286, 0, 8000000, 1, 0, 0, 0},
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{"286/6", CPU_286, 0, 6000000, 1, 0, 0, 0, 0},
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{"286/8", CPU_286, 0, 8000000, 1, 0, 0, 0, 0},
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{"", -1, 0, 0, 0, 0}
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};
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CPU cpus_i386[] =
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{
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/*i386*/
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{"i386SX/16", CPU_386SX, 0, 16000000, 1, 0x2308, 0, 0},
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{"i386SX/20", CPU_386SX, 1, 20000000, 1, 0x2308, 0, 0},
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{"i386SX/25", CPU_386SX, 2, 25000000, 1, 0x2308, 0, 0},
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{"i386SX/33", CPU_386SX, 3, 33333333, 1, 0x2308, 0, 0},
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{"i386DX/16", CPU_386DX, 0, 16000000, 1, 0x0308, 0, 0},
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{"i386DX/20", CPU_386DX, 1, 20000000, 1, 0x0308, 0, 0},
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{"i386DX/25", CPU_386DX, 2, 25000000, 1, 0x0308, 0, 0},
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{"i386DX/33", CPU_386DX, 3, 33333333, 1, 0x0308, 0, 0},
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{"i386SX/16", CPU_386SX, 0, 16000000, 1, 0x2308, 0, 0, 0},
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{"i386SX/20", CPU_386SX, 1, 20000000, 1, 0x2308, 0, 0, 0},
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{"i386SX/25", CPU_386SX, 2, 25000000, 1, 0x2308, 0, 0, 0},
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{"i386SX/33", CPU_386SX, 3, 33333333, 1, 0x2308, 0, 0, 0},
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{"i386DX/16", CPU_386DX, 0, 16000000, 1, 0x0308, 0, 0, 0},
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{"i386DX/20", CPU_386DX, 1, 20000000, 1, 0x0308, 0, 0, 0},
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{"i386DX/25", CPU_386DX, 2, 25000000, 1, 0x0308, 0, 0, 0},
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{"i386DX/33", CPU_386DX, 3, 33333333, 1, 0x0308, 0, 0, 0},
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{"", -1, 0, 0, 0}
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};
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CPU cpus_acer[] =
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{
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/*i386*/
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{"i386SX/25", CPU_386SX, 2, 25000000, 1, 0x2308, 0, 0},
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{"i386SX/25", CPU_386SX, 2, 25000000, 1, 0x2308, 0, 0, 0},
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{"", -1, 0, 0, 0}
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};
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CPU cpus_Am386[] =
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{
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/*Am386*/
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{"Am386SX/16", CPU_386SX, 0, 16000000, 1, 0x2308, 0, 0},
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{"Am386SX/20", CPU_386SX, 1, 20000000, 1, 0x2308, 0, 0},
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{"Am386SX/25", CPU_386SX, 2, 25000000, 1, 0x2308, 0, 0},
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{"Am386SX/33", CPU_386SX, 3, 33333333, 1, 0x2308, 0, 0},
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{"Am386SX/40", CPU_386SX, 4, 40000000, 1, 0x2308, 0, 0},
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{"Am386DX/25", CPU_386DX, 2, 25000000, 1, 0x0308, 0, 0},
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{"Am386DX/33", CPU_386DX, 3, 33333333, 1, 0x0308, 0, 0},
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{"Am386DX/40", CPU_386DX, 4, 40000000, 1, 0x0308, 0, 0},
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{"Am386SX/16", CPU_386SX, 0, 16000000, 1, 0x2308, 0, 0, 0},
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{"Am386SX/20", CPU_386SX, 1, 20000000, 1, 0x2308, 0, 0, 0},
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{"Am386SX/25", CPU_386SX, 2, 25000000, 1, 0x2308, 0, 0, 0},
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{"Am386SX/33", CPU_386SX, 3, 33333333, 1, 0x2308, 0, 0, 0},
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{"Am386SX/40", CPU_386SX, 4, 40000000, 1, 0x2308, 0, 0, 0},
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{"Am386DX/25", CPU_386DX, 2, 25000000, 1, 0x0308, 0, 0, 0},
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{"Am386DX/33", CPU_386DX, 3, 33333333, 1, 0x0308, 0, 0, 0},
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{"Am386DX/40", CPU_386DX, 4, 40000000, 1, 0x0308, 0, 0, 0},
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{"", -1, 0, 0, 0}
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};
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CPU cpus_486SDLC[] =
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{
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/*Cx486SLC/DLC*/
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{"Cx486SLC/20", CPU_486SLC, 1, 20000000, 1, 0, 0, 0x0000},
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{"Cx486SLC/25", CPU_486SLC, 2, 25000000, 1, 0, 0, 0x0000},
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{"Cx486SLC/33", CPU_486SLC, 3, 33333333, 1, 0, 0, 0x0000},
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{"Cx486SRx2/32", CPU_486SLC, 3, 32000000, 2, 0, 0, 0x0006},
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{"Cx486SRx2/40", CPU_486SLC, 4, 40000000, 2, 0, 0, 0x0006},
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{"Cx486SRx2/50", CPU_486SLC, 5, 50000000, 2, 0, 0, 0x0006},
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{"Cx486DLC/25", CPU_486DLC, 2, 25000000, 1, 0, 0, 0x0001},
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{"Cx486DLC/33", CPU_486DLC, 3, 33333333, 1, 0, 0, 0x0001},
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{"Cx486DLC/40", CPU_486DLC, 4, 40000000, 1, 0, 0, 0x0001},
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{"Cx486DRx2/32", CPU_486DLC, 3, 32000000, 2, 0, 0, 0x0007},
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{"Cx486DRx2/40", CPU_486DLC, 4, 40000000, 2, 0, 0, 0x0007},
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{"Cx486DRx2/50", CPU_486DLC, 5, 50000000, 2, 0, 0, 0x0007},
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{"Cx486DRx2/66", CPU_486DLC, 6, 66666666, 2, 0, 0, 0x0007},
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{"Cx486SLC/20", CPU_486SLC, 1, 20000000, 1, 0, 0, 0x0000, 0},
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{"Cx486SLC/25", CPU_486SLC, 2, 25000000, 1, 0, 0, 0x0000, 0},
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{"Cx486SLC/33", CPU_486SLC, 3, 33333333, 1, 0, 0, 0x0000, 0},
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{"Cx486SRx2/32", CPU_486SLC, 3, 32000000, 2, 0, 0, 0x0006, 0},
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{"Cx486SRx2/40", CPU_486SLC, 4, 40000000, 2, 0, 0, 0x0006, 0},
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{"Cx486SRx2/50", CPU_486SLC, 5, 50000000, 2, 0, 0, 0x0006, 0},
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{"Cx486DLC/25", CPU_486DLC, 2, 25000000, 1, 0, 0, 0x0001, 0},
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{"Cx486DLC/33", CPU_486DLC, 3, 33333333, 1, 0, 0, 0x0001, 0},
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{"Cx486DLC/40", CPU_486DLC, 4, 40000000, 1, 0, 0, 0x0001, 0},
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{"Cx486DRx2/32", CPU_486DLC, 3, 32000000, 2, 0, 0, 0x0007, 0},
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{"Cx486DRx2/40", CPU_486DLC, 4, 40000000, 2, 0, 0, 0x0007, 0},
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{"Cx486DRx2/50", CPU_486DLC, 5, 50000000, 2, 0, 0, 0x0007, 0},
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{"Cx486DRx2/66", CPU_486DLC, 6, 66666666, 2, 0, 0, 0x0007, 0},
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{"", -1, 0, 0, 0}
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};
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CPU cpus_i486[] =
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{
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/*i486*/
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{"i486SX/16", CPU_i486SX, 0, 16000000, 1, 0x42a, 0, 0},
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{"i486SX/20", CPU_i486SX, 1, 20000000, 1, 0x42a, 0, 0},
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{"i486SX/25", CPU_i486SX, 2, 25000000, 1, 0x42a, 0, 0},
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{"i486SX/33", CPU_i486SX, 3, 33333333, 1, 0x42a, 0, 0},
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{"i486SX2/50", CPU_i486SX, 5, 50000000, 2, 0x45b, 0, 0},
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{"i486DX/25", CPU_i486DX, 2, 25000000, 1, 0x404, 0, 0},
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{"i486DX/33", CPU_i486DX, 3, 33333333, 1, 0x404, 0, 0},
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{"i486DX/50", CPU_i486DX, 5, 50000000, 1, 0x404, 0, 0},
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{"i486DX2/40", CPU_i486DX, 4, 40000000, 2, 0x430, 0, 0},
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{"i486DX2/50", CPU_i486DX, 5, 50000000, 2, 0x430, 0, 0},
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{"i486DX2/66", CPU_i486DX, 6, 66666666, 2, 0x430, 0, 0},
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{"iDX4/75", CPU_i486DX, 7, 75000000, 3, 0x481, 0x481, 0}, /*CPUID available on DX4, >= 75 MHz*/
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{"iDX4/100", CPU_i486DX,10, 100000000, 3, 0x481, 0x481, 0}, /*Is on some real Intel DX2s, limit here is pretty arbitary*/
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#ifdef DYNAREC
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{"Pentium OverDrive/63", CPU_PENTIUM, 6, 62500000, 3, 0x1531, 0x1531, 0},
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{"Pentium OverDrive/83", CPU_PENTIUM, 8, 83333333, 3, 0x1532, 0x1532, 0},
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#endif
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{"i486SX/16", CPU_i486SX, 0, 16000000, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC},
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{"i486SX/20", CPU_i486SX, 1, 20000000, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC},
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{"i486SX/25", CPU_i486SX, 2, 25000000, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC},
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{"i486SX/33", CPU_i486SX, 3, 33333333, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC},
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{"i486SX2/50", CPU_i486SX, 5, 50000000, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC},
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{"i486DX/25", CPU_i486DX, 2, 25000000, 1, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC},
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{"i486DX/33", CPU_i486DX, 3, 33333333, 1, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC},
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{"i486DX/50", CPU_i486DX, 5, 50000000, 1, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC},
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{"i486DX2/40", CPU_i486DX, 4, 40000000, 2, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC},
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{"i486DX2/50", CPU_i486DX, 5, 50000000, 2, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC},
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{"i486DX2/66", CPU_i486DX, 6, 66666666, 2, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC},
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{"iDX4/75", CPU_i486DX, 7, 75000000, 3, 0x481, 0x481, 0, CPU_SUPPORTS_DYNAREC}, /*CPUID available on DX4, >= 75 MHz*/
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{"iDX4/100", CPU_i486DX,10, 100000000, 3, 0x481, 0x481, 0, CPU_SUPPORTS_DYNAREC}, /*Is on some real Intel DX2s, limit here is pretty arbitary*/
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{"Pentium OverDrive/63", CPU_PENTIUM, 6, 62500000, 3, 0x1531, 0x1531, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
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{"Pentium OverDrive/83", CPU_PENTIUM, 8, 83333333, 3, 0x1532, 0x1532, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
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{"", -1, 0, 0, 0}
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};
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CPU cpus_Am486[] =
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{
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/*Am486/5x86*/
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{"Am486SX/33", CPU_Am486SX, 3, 33333333, 1, 0x42a, 0, 0},
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{"Am486SX/40", CPU_Am486SX, 4, 40000000, 1, 0x42a, 0, 0},
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{"Am486SX2/50", CPU_Am486SX, 5, 50000000, 2, 0x45b, 0x45b, 0}, /*CPUID available on SX2, DX2, DX4, 5x86, >= 50 MHz*/
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{"Am486SX2/66", CPU_Am486SX, 6, 66666666, 2, 0x45b, 0x45b, 0}, /*Isn't on all real AMD SX2s and DX2s, availability here is pretty arbitary (and distinguishes them from the Intel chips)*/
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{"Am486DX/33", CPU_Am486DX, 3, 33333333, 1, 0x430, 0, 0},
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{"Am486DX/40", CPU_Am486DX, 4, 40000000, 1, 0x430, 0, 0},
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{"Am486DX2/50", CPU_Am486DX, 5, 50000000, 2, 0x470, 0x470, 0},
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{"Am486DX2/66", CPU_Am486DX, 6, 66666666, 2, 0x470, 0x470, 0},
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{"Am486DX2/80", CPU_Am486DX, 8, 80000000, 2, 0x470, 0x470, 0},
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{"Am486DX4/75", CPU_Am486DX, 7, 75000000, 3, 0x482, 0x482, 0},
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{"Am486DX4/90", CPU_Am486DX, 9, 90000000, 3, 0x482, 0x482, 0},
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{"Am486DX4/100", CPU_Am486DX, 10, 100000000, 3, 0x482, 0x482, 0},
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{"Am486DX4/120", CPU_Am486DX, 11, 120000000, 3, 0x482, 0x482, 0},
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{"Am5x86/P75", CPU_Am486DX, 12, 133333333, 4, 0x4e0, 0x4e0, 0},
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{"Am5x86/P75+", CPU_Am486DX, 13, 150000000, 4, 0x4e0, 0x4e0, 0},
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{"Am486SX/33", CPU_Am486SX, 3, 33333333, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC},
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{"Am486SX/40", CPU_Am486SX, 4, 40000000, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC},
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{"Am486SX2/50", CPU_Am486SX, 5, 50000000, 2, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC}, /*CPUID available on SX2, DX2, DX4, 5x86, >= 50 MHz*/
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{"Am486SX2/66", CPU_Am486SX, 6, 66666666, 2, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC}, /*Isn't on all real AMD SX2s and DX2s, availability here is pretty arbitary (and distinguishes them from the Intel chips)*/
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{"Am486DX/33", CPU_Am486DX, 3, 33333333, 1, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC},
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{"Am486DX/40", CPU_Am486DX, 4, 40000000, 1, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC},
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{"Am486DX2/50", CPU_Am486DX, 5, 50000000, 2, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC},
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{"Am486DX2/66", CPU_Am486DX, 6, 66666666, 2, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC},
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{"Am486DX2/80", CPU_Am486DX, 8, 80000000, 2, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC},
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{"Am486DX4/75", CPU_Am486DX, 7, 75000000, 3, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC},
|
||||
{"Am486DX4/90", CPU_Am486DX, 9, 90000000, 3, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC},
|
||||
{"Am486DX4/100", CPU_Am486DX, 10, 100000000, 3, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC},
|
||||
{"Am486DX4/120", CPU_Am486DX, 11, 120000000, 3, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC},
|
||||
{"Am5x86/P75", CPU_Am486DX, 12, 133333333, 4, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC},
|
||||
{"Am5x86/P75+", CPU_Am486DX, 13, 150000000, 4, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC},
|
||||
{"", -1, 0, 0, 0}
|
||||
};
|
||||
|
||||
CPU cpus_Cx486[] =
|
||||
{
|
||||
/*Cx486/5x86*/
|
||||
{"Cx486S/25", CPU_Cx486S, 2, 25000000, 1, 0x420, 0, 0x0010},
|
||||
{"Cx486S/33", CPU_Cx486S, 3, 33333333, 1, 0x420, 0, 0x0010},
|
||||
{"Cx486S/40", CPU_Cx486S, 4, 40000000, 1, 0x420, 0, 0x0010},
|
||||
{"Cx486DX/33", CPU_Cx486DX, 3, 33333333, 1, 0x430, 0, 0x051a},
|
||||
{"Cx486DX/40", CPU_Cx486DX, 4, 40000000, 1, 0x430, 0, 0x051a},
|
||||
{"Cx486DX2/50", CPU_Cx486DX, 5, 50000000, 2, 0x430, 0, 0x081b},
|
||||
{"Cx486DX2/66", CPU_Cx486DX, 6, 66666666, 2, 0x430, 0, 0x0b1b},
|
||||
{"Cx486DX2/80", CPU_Cx486DX, 8, 80000000, 2, 0x430, 0, 0x311b},
|
||||
{"Cx486DX4/75", CPU_Cx486DX, 7, 75000000, 3, 0x480, 0, 0x361f},
|
||||
{"Cx486DX4/100", CPU_Cx486DX, 10, 100000000, 3, 0x480, 0, 0x361f},
|
||||
{"Cx5x86/100", CPU_Cx5x86, 10, 100000000, 3, 0x480, 0, 0x002f},
|
||||
{"Cx5x86/120", CPU_Cx5x86, 11, 120000000, 3, 0x480, 0, 0x002f},
|
||||
{"Cx5x86/133", CPU_Cx5x86, 12, 133333333, 4, 0x480, 0, 0x002f},
|
||||
{"Cx486S/25", CPU_Cx486S, 2, 25000000, 1, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC},
|
||||
{"Cx486S/33", CPU_Cx486S, 3, 33333333, 1, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC},
|
||||
{"Cx486S/40", CPU_Cx486S, 4, 40000000, 1, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC},
|
||||
{"Cx486DX/33", CPU_Cx486DX, 3, 33333333, 1, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC},
|
||||
{"Cx486DX/40", CPU_Cx486DX, 4, 40000000, 1, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC},
|
||||
{"Cx486DX2/50", CPU_Cx486DX, 5, 50000000, 2, 0x430, 0, 0x081b, CPU_SUPPORTS_DYNAREC},
|
||||
{"Cx486DX2/66", CPU_Cx486DX, 6, 66666666, 2, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC},
|
||||
{"Cx486DX2/80", CPU_Cx486DX, 8, 80000000, 2, 0x430, 0, 0x311b, CPU_SUPPORTS_DYNAREC},
|
||||
{"Cx486DX4/75", CPU_Cx486DX, 7, 75000000, 3, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC},
|
||||
{"Cx486DX4/100", CPU_Cx486DX, 10, 100000000, 3, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC},
|
||||
{"Cx5x86/100", CPU_Cx5x86, 10, 100000000, 3, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC},
|
||||
{"Cx5x86/120", CPU_Cx5x86, 11, 120000000, 3, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC},
|
||||
{"Cx5x86/133", CPU_Cx5x86, 12, 133333333, 4, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC},
|
||||
{"", -1, 0, 0, 0}
|
||||
};
|
||||
|
||||
CPU cpus_WinChip[] =
|
||||
{
|
||||
/*IDT WinChip*/
|
||||
{"WinChip 75", CPU_WINCHIP, 7, 75000000, 2, 0x540, 0x540, 0},
|
||||
{"WinChip 90", CPU_WINCHIP, 9, 90000000, 2, 0x540, 0x540, 0},
|
||||
{"WinChip 100", CPU_WINCHIP, 10, 100000000, 2, 0x540, 0x540, 0},
|
||||
{"WinChip 120", CPU_WINCHIP, 11, 120000000, 2, 0x540, 0x540, 0},
|
||||
{"WinChip 133", CPU_WINCHIP, 12, 133333333, 2, 0x540, 0x540, 0},
|
||||
{"WinChip 150", CPU_WINCHIP, 13, 150000000, 3, 0x540, 0x540, 0},
|
||||
{"WinChip 166", CPU_WINCHIP, 15, 166666666, 3, 0x540, 0x540, 0},
|
||||
{"WinChip 180", CPU_WINCHIP, 16, 180000000, 3, 0x540, 0x540, 0},
|
||||
{"WinChip 200", CPU_WINCHIP, 17, 200000000, 3, 0x540, 0x540, 0},
|
||||
{"WinChip 225", CPU_WINCHIP, 17, 225000000, 3, 0x540, 0x540, 0},
|
||||
{"WinChip 240", CPU_WINCHIP, 17, 240000000, 6, 0x540, 0x540, 0},
|
||||
{"WinChip 75", CPU_WINCHIP, 7, 75000000, 2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC},
|
||||
{"WinChip 90", CPU_WINCHIP, 9, 90000000, 2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC},
|
||||
{"WinChip 100", CPU_WINCHIP, 10, 100000000, 2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC},
|
||||
{"WinChip 120", CPU_WINCHIP, 11, 120000000, 2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC},
|
||||
{"WinChip 133", CPU_WINCHIP, 12, 133333333, 2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC},
|
||||
{"WinChip 150", CPU_WINCHIP, 13, 150000000, 3, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC},
|
||||
{"WinChip 166", CPU_WINCHIP, 15, 166666666, 3, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC},
|
||||
{"WinChip 180", CPU_WINCHIP, 16, 180000000, 3, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC},
|
||||
{"WinChip 200", CPU_WINCHIP, 17, 200000000, 3, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC},
|
||||
{"WinChip 225", CPU_WINCHIP, 17, 225000000, 3, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC},
|
||||
{"WinChip 240", CPU_WINCHIP, 17, 240000000, 6, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC},
|
||||
{"", -1, 0, 0, 0}
|
||||
};
|
||||
#ifdef DYNAREC
|
||||
|
||||
CPU cpus_Pentium5V[] =
|
||||
{
|
||||
/*Intel Pentium (5V, socket 4)*/
|
||||
{"Pentium 60", CPU_PENTIUM, 6, 60000000, 1, 0x52c, 0x52c, 0},
|
||||
{"Pentium 66", CPU_PENTIUM, 6, 66666666, 1, 0x52c, 0x52c, 0},
|
||||
{"Pentium 60", CPU_PENTIUM, 6, 60000000, 1, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
|
||||
{"Pentium 66", CPU_PENTIUM, 6, 66666666, 1, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
|
||||
{"", -1, 0, 0, 0}
|
||||
};
|
||||
|
||||
CPU cpus_Pentium[] =
|
||||
{
|
||||
/*Intel Pentium*/
|
||||
{"Pentium 75", CPU_PENTIUM, 7, 75000000, 2, 0x52c, 0x52c, 0},
|
||||
{"Pentium 90", CPU_PENTIUM, 9, 90000000, 2, 0x52c, 0x52c, 0},
|
||||
{"Pentium 100", CPU_PENTIUM, 10, 100000000, 2, 0x52c, 0x52c, 0},
|
||||
{"Pentium 120", CPU_PENTIUM, 11, 120000000, 2, 0x52c, 0x52c, 0},
|
||||
{"Pentium 133", CPU_PENTIUM, 12, 133333333, 2, 0x52c, 0x52c, 0},
|
||||
{"Pentium 150", CPU_PENTIUM, 12, 150000000, 3, 0x52c, 0x52c, 0},
|
||||
{"Pentium 166", CPU_PENTIUM, 12, 166666666, 3, 0x52c, 0x52c, 0},
|
||||
{"Pentium 200", CPU_PENTIUM, 12, 200000000, 3, 0x52c, 0x52c, 0},
|
||||
{"Pentium MMX 166", CPU_PENTIUMMMX, 12, 166666666, 3, 0x543, 0x543, 0},
|
||||
{"Pentium MMX 200", CPU_PENTIUMMMX, 12, 200000000, 3, 0x543, 0x543, 0},
|
||||
{"Pentium MMX 233", CPU_PENTIUMMMX, 12, 233333333, 4, 0x543, 0x543, 0},
|
||||
{"Mobile Pentium MMX 120", CPU_PENTIUMMMX, 12, 120000000, 2, 0x543, 0x543, 0},
|
||||
{"Mobile Pentium MMX 133", CPU_PENTIUMMMX, 12, 133333333, 2, 0x543, 0x543, 0},
|
||||
{"Mobile Pentium MMX 150", CPU_PENTIUMMMX, 12, 150000000, 3, 0x544, 0x544, 0},
|
||||
{"Mobile Pentium MMX 166", CPU_PENTIUMMMX, 12, 166666666, 3, 0x544, 0x544, 0},
|
||||
{"Mobile Pentium MMX 200", CPU_PENTIUMMMX, 12, 200000000, 3, 0x581, 0x581, 0},
|
||||
{"Mobile Pentium MMX 233", CPU_PENTIUMMMX, 12, 233333333, 4, 0x581, 0x581, 0},
|
||||
{"Mobile Pentium MMX 266", CPU_PENTIUMMMX, 12, 266666666, 4, 0x582, 0x582, 0},
|
||||
{"Mobile Pentium MMX 300", CPU_PENTIUMMMX, 12, 300000000, 5, 0x582, 0x582, 0},
|
||||
{"Pentium 75", CPU_PENTIUM, 7, 75000000, 2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
|
||||
{"Pentium 90", CPU_PENTIUM, 9, 90000000, 2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
|
||||
{"Pentium 100", CPU_PENTIUM, 10, 100000000, 2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
|
||||
{"Pentium 120", CPU_PENTIUM, 11, 120000000, 2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
|
||||
{"Pentium 133", CPU_PENTIUM, 12, 133333333, 2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
|
||||
{"Pentium 150", CPU_PENTIUM, 12, 150000000, 3, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
|
||||
{"Pentium 166", CPU_PENTIUM, 12, 166666666, 3, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
|
||||
{"Pentium 200", CPU_PENTIUM, 12, 200000000, 3, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
|
||||
{"Pentium MMX 166", CPU_PENTIUMMMX, 12, 166666666, 3, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
|
||||
{"Pentium MMX 200", CPU_PENTIUMMMX, 12, 200000000, 3, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
|
||||
{"Pentium MMX 233", CPU_PENTIUMMMX, 12, 233333333, 4, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
|
||||
{"Mobile Pentium MMX 120", CPU_PENTIUMMMX, 12, 120000000, 2, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
|
||||
{"Mobile Pentium MMX 133", CPU_PENTIUMMMX, 12, 133333333, 2, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
|
||||
{"Mobile Pentium MMX 150", CPU_PENTIUMMMX, 12, 150000000, 3, 0x544, 0x544, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
|
||||
{"Mobile Pentium MMX 166", CPU_PENTIUMMMX, 12, 166666666, 3, 0x544, 0x544, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
|
||||
{"Mobile Pentium MMX 200", CPU_PENTIUMMMX, 12, 200000000, 3, 0x581, 0x581, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
|
||||
{"Mobile Pentium MMX 233", CPU_PENTIUMMMX, 12, 233333333, 4, 0x581, 0x581, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
|
||||
{"Mobile Pentium MMX 266", CPU_PENTIUMMMX, 12, 266666666, 4, 0x582, 0x582, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
|
||||
{"Mobile Pentium MMX 300", CPU_PENTIUMMMX, 12, 300000000, 5, 0x582, 0x582, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC},
|
||||
{"", -1, 0, 0, 0}
|
||||
};
|
||||
#endif
|
||||
|
||||
void cpu_set_edx()
|
||||
{
|
||||
EDX = models[model].cpu[cpu_manufacturer].cpus[cpu].edx_reset;
|
||||
|
|
@ -372,12 +367,8 @@ void cpu_set()
|
|||
pclog("hasfpu - %i\n",hasfpu);
|
||||
pclog("is486 - %i %i\n",is486,cpu_s->cpu_type);
|
||||
|
||||
#ifdef DYNAREC
|
||||
x86_setopcodes(ops_386, ops_386_0f, dynarec_ops_386, dynarec_ops_386_0f);
|
||||
#else
|
||||
x86_setopcodes(ops_386, ops_386_0f);
|
||||
#endif
|
||||
#ifdef DYNAREC
|
||||
|
||||
if (hasfpu)
|
||||
{
|
||||
x86_dynarec_opcodes_d8_a16 = dynarec_ops_fpu_d8_a16;
|
||||
|
|
@ -417,7 +408,7 @@ void cpu_set()
|
|||
x86_dynarec_opcodes_df_a16 = dynarec_ops_nofpu_a32;
|
||||
}
|
||||
codegen_timing_set(&codegen_timing_486);
|
||||
#endif
|
||||
|
||||
if (hasfpu)
|
||||
{
|
||||
x86_opcodes_d8_a16 = ops_fpu_d8_a16;
|
||||
|
|
@ -466,11 +457,7 @@ void cpu_set()
|
|||
break;
|
||||
|
||||
case CPU_286:
|
||||
#ifdef DYNAREC
|
||||
x86_setopcodes(ops_286, ops_286_0f, dynarec_ops_286, dynarec_ops_286_0f);
|
||||
#else
|
||||
x86_setopcodes(ops_286, ops_286_0f);
|
||||
#endif
|
||||
timing_rr = 2; /*register dest - register src*/
|
||||
timing_rm = 7; /*register dest - memory src*/
|
||||
timing_mr = 7; /*memory dest - register src*/
|
||||
|
|
@ -583,11 +570,7 @@ void cpu_set()
|
|||
break;
|
||||
|
||||
case CPU_WINCHIP:
|
||||
#ifdef DYNAREC
|
||||
x86_setopcodes(ops_386, ops_winchip_0f, dynarec_ops_386, dynarec_ops_winchip_0f);
|
||||
#else
|
||||
x86_setopcodes(ops_386, ops_winchip_0f);
|
||||
#endif
|
||||
timing_rr = 1; /*register dest - register src*/
|
||||
timing_rm = 2; /*register dest - memory src*/
|
||||
timing_mr = 3; /*memory dest - register src*/
|
||||
|
|
@ -604,7 +587,6 @@ void cpu_set()
|
|||
cpu_CR4_mask = CR4_TSD | CR4_DE | CR4_MCE | CR4_PCE;
|
||||
break;
|
||||
|
||||
#ifdef DYNAREC
|
||||
case CPU_PENTIUM:
|
||||
x86_setopcodes(ops_386, ops_pentium_0f, dynarec_ops_386, dynarec_ops_pentium_0f);
|
||||
timing_rr = 1; /*register dest - register src*/
|
||||
|
|
@ -644,7 +626,6 @@ void cpu_set()
|
|||
cpu_CR4_mask = CR4_TSD | CR4_DE | CR4_MCE | CR4_PCE;
|
||||
codegen_timing_set(&codegen_timing_pentium);
|
||||
break;
|
||||
#endif
|
||||
|
||||
default:
|
||||
fatal("cpu_set : unknown CPU type %i\n", cpu_s->cpu_type);
|
||||
|
|
@ -736,7 +717,7 @@ void cpu_CPUID()
|
|||
else
|
||||
EAX = 0;
|
||||
break;
|
||||
#ifdef DYNAREC
|
||||
|
||||
case CPU_PENTIUM:
|
||||
if (!EAX)
|
||||
{
|
||||
|
|
@ -772,7 +753,6 @@ void cpu_CPUID()
|
|||
else
|
||||
EAX = 0;
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -809,7 +789,7 @@ void cpu_RDMSR()
|
|||
break;
|
||||
}
|
||||
break;
|
||||
#ifdef DYNAREC
|
||||
|
||||
case CPU_PENTIUM:
|
||||
case CPU_PENTIUMMMX:
|
||||
EAX = EDX = 0;
|
||||
|
|
@ -821,7 +801,6 @@ void cpu_RDMSR()
|
|||
break;
|
||||
}
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -860,7 +839,7 @@ void cpu_WRMSR()
|
|||
break;
|
||||
}
|
||||
break;
|
||||
#ifdef DYNAREC
|
||||
|
||||
case CPU_PENTIUM:
|
||||
case CPU_PENTIUMMMX:
|
||||
switch (ECX)
|
||||
|
|
@ -870,7 +849,6 @@ void cpu_WRMSR()
|
|||
break;
|
||||
}
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -897,7 +875,6 @@ uint8_t cyrix_read(uint16_t addr, void *priv)
|
|||
return 0xff;
|
||||
}
|
||||
|
||||
#ifdef DYNAREC
|
||||
void x86_setopcodes(OpFn *opcodes, OpFn *opcodes_0f, OpFn *dynarec_opcodes, OpFn *dynarec_opcodes_0f)
|
||||
{
|
||||
x86_opcodes = opcodes;
|
||||
|
|
@ -905,10 +882,3 @@ void x86_setopcodes(OpFn *opcodes, OpFn *opcodes_0f, OpFn *dynarec_opcodes, OpFn
|
|||
x86_dynarec_opcodes = dynarec_opcodes;
|
||||
x86_dynarec_opcodes_0f = dynarec_opcodes_0f;
|
||||
}
|
||||
#else
|
||||
void x86_setopcodes(OpFn *opcodes, OpFn *opcodes_0f)
|
||||
{
|
||||
x86_opcodes = opcodes;
|
||||
x86_opcodes_0f = opcodes_0f;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in a new issue