Add recompiled versions of mem->reg, reg->mem and imm->mem versions of MOV.
This commit is contained in:
SarahW
parent
91143d3c68
commit
f27b7f757a
30 changed files with 5225 additions and 2160 deletions
587
src/codegen_backend_arm_ops.c
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587
src/codegen_backend_arm_ops.c
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#ifdef __ARM_EABI__
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#include "ibm.h"
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#include "codegen.h"
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#include "codegen_backend.h"
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#include "codegen_backend_arm_defs.h"
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#include "codegen_backend_arm_ops.h"
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static inline void codegen_addlong(codeblock_t *block, uint32_t val)
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{
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*(uint32_t *)&block->data[block_pos] = val;
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block_pos += 4;
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if (block_pos >= BLOCK_MAX)
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{
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fatal("codegen_addlong over! %i\n", block_pos);
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CPU_BLOCK_END();
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}
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}
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#define Rm(x) (x)
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#define Rd(x) ((x) << 12)
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#define Rn(x) ((x) << 16)
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#define DATA_OFFSET_UP (1 << 23)
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#define DATA_OFFSET_DOWN (0 << 23)
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#define COND_SHIFT 28
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#define COND_EQ (0x0 << COND_SHIFT)
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#define COND_NE (0x1 << COND_SHIFT)
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#define COND_AL (0xe << COND_SHIFT)
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#define OPCODE_SHIFT 20
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#define OPCODE_ADD_IMM (0x28 << OPCODE_SHIFT)
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#define OPCODE_ADD_REG (0x08 << OPCODE_SHIFT)
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#define OPCODE_AND_IMM (0x20 << OPCODE_SHIFT)
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#define OPCODE_AND_REG (0x00 << OPCODE_SHIFT)
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#define OPCODE_B (0xa0 << OPCODE_SHIFT)
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#define OPCODE_BIC_IMM (0x3c << OPCODE_SHIFT)
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#define OPCODE_BIC_REG (0x1c << OPCODE_SHIFT)
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#define OPCODE_BL (0xb0 << OPCODE_SHIFT)
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#define OPCODE_CMN_IMM (0x37 << OPCODE_SHIFT)
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#define OPCODE_CMN_REG (0x17 << OPCODE_SHIFT)
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#define OPCODE_CMP_IMM (0x35 << OPCODE_SHIFT)
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#define OPCODE_CMP_REG (0x15 << OPCODE_SHIFT)
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#define OPCODE_EOR_IMM (0x22 << OPCODE_SHIFT)
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#define OPCODE_EOR_REG (0x02 << OPCODE_SHIFT)
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#define OPCODE_LDMIA_WB (0x8b << OPCODE_SHIFT)
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#define OPCODE_LDR_IMM (0x51 << OPCODE_SHIFT)
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#define OPCODE_LDR_IMM_POST (0x41 << OPCODE_SHIFT)
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#define OPCODE_LDR_REG (0x79 << OPCODE_SHIFT)
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#define OPCODE_LDRB_IMM (0x55 << OPCODE_SHIFT)
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#define OPCODE_LDRB_REG (0x7d << OPCODE_SHIFT)
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#define OPCODE_MOV_IMM (0x3a << OPCODE_SHIFT)
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#define OPCODE_MOVT_IMM (0x34 << OPCODE_SHIFT)
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#define OPCODE_MOVW_IMM (0x30 << OPCODE_SHIFT)
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#define OPCODE_MOV_REG (0x1a << OPCODE_SHIFT)
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#define OPCODE_MVN_REG (0x1e << OPCODE_SHIFT)
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#define OPCODE_ORR_IMM (0x38 << OPCODE_SHIFT)
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#define OPCODE_ORR_REG (0x18 << OPCODE_SHIFT)
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#define OPCODE_RSB_REG (0x06 << OPCODE_SHIFT)
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#define OPCODE_STMDB_WB (0x92 << OPCODE_SHIFT)
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#define OPCODE_STR_IMM (0x50 << OPCODE_SHIFT)
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#define OPCODE_STR_IMM_WB (0x52 << OPCODE_SHIFT)
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#define OPCODE_STR_REG (0x78 << OPCODE_SHIFT)
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#define OPCODE_STRB_IMM (0x54 << OPCODE_SHIFT)
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#define OPCODE_STRB_REG (0x7c << OPCODE_SHIFT)
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#define OPCODE_SUB_IMM (0x24 << OPCODE_SHIFT)
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#define OPCODE_SUB_REG (0x04 << OPCODE_SHIFT)
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#define OPCODE_TST_IMM (0x31 << OPCODE_SHIFT)
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#define OPCODE_TST_REG (0x11 << OPCODE_SHIFT)
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#define OPCODE_BFI 0xe7c00010
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#define OPCODE_BLX 0xe12fff30
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#define OPCODE_LDRH_REG 0xe19000b0
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#define OPCODE_STRH_REG 0xe18000b0
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#define OPCODE_UADD8 0xe6500f90
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#define OPCODE_UADD16 0xe6500f10
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#define OPCODE_USUB8 0xe6500ff0
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#define OPCODE_USUB16 0xe6500f70
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#define OPCODE_UXTB 0xe6ef0070
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#define OPCODE_UXTH 0xe6ff0070
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#define B_OFFSET(x) (((x) >> 2) & 0xffffff)
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#define SHIFT_TYPE_SHIFT 5
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#define SHIFT_TYPE_LSL (0 << SHIFT_TYPE_SHIFT)
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#define SHIFT_TYPE_LSR (1 << SHIFT_TYPE_SHIFT)
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#define SHIFT_TYPE_ASR (2 << SHIFT_TYPE_SHIFT)
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#define SHIFT_TYPE_ROR (3 << SHIFT_TYPE_SHIFT)
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#define SHIFT_TYPE_IMM (0 << 4)
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#define SHIFT_TYPE_REG (1 << 4)
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#define SHIFT_IMM_SHIFT 7
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#define SHIFT_LSL_IMM(x) (SHIFT_TYPE_LSL | SHIFT_TYPE_IMM | ((x) << SHIFT_IMM_SHIFT))
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#define SHIFT_LSR_IMM(x) (SHIFT_TYPE_LSR | SHIFT_TYPE_IMM | ((x) << SHIFT_IMM_SHIFT))
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#define BFI_lsb(lsb) ((lsb) << 7)
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#define BFI_msb(msb) ((msb) << 16)
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#define UXTB_ROTATE(rotate) (((rotate) >> 3) << 10)
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#define MOVT_IMM(imm) (((imm) & 0xfff) | (((imm) & 0xf000) << 4))
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#define MOVW_IMM(imm) (((imm) & 0xfff) | (((imm) & 0xf000) << 4))
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static int literal_offset = 0;
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void codegen_reset_literal_pool(codeblock_t *block)
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{
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literal_offset = 0;
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}
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int add_literal(codeblock_t *block, uint32_t data)
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{
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int c;
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if (literal_offset >= 4096)
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fatal("add_literal - literal pool full\n");
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/*Search for pre-existing value*/
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for (c = 0; c < literal_offset; c += 4)
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{
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if (*(uint32_t *)&block->data[ARM_LITERAL_POOL_OFFSET + c] == data)
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return c;
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}
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*(uint32_t *)&block->data[ARM_LITERAL_POOL_OFFSET + literal_offset] = data;
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literal_offset += 4;
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return literal_offset - 4;
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}
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static inline uint32_t arm_data_offset(int offset)
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{
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if (offset < -0xffc || offset > 0xffc)
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fatal("arm_data_offset out of range - %i\n", offset);
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if (offset >= 0)
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return offset | DATA_OFFSET_UP;
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return (-offset) | DATA_OFFSET_DOWN;
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}
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static inline int get_arm_imm(uint32_t imm_data, uint32_t *arm_imm)
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{
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int shift = 0;
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//pclog("get_arm_imm - imm_data=%08x\n", imm_data);
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if (!(imm_data & 0xffff))
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{
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shift += 16;
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imm_data >>= 16;
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}
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if (!(imm_data & 0xff))
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{
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shift += 8;
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imm_data >>= 8;
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}
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if (!(imm_data & 0xf))
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{
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shift += 4;
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imm_data >>= 4;
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}
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if (!(imm_data & 0x3))
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{
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shift += 2;
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imm_data >>= 2;
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}
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if (imm_data > 0xff) /*Note - should handle rotation round the word*/
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return 0;
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//pclog(" imm_data=%02x shift=%i\n", imm_data, shift);
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*arm_imm = imm_data | ((((32 - shift) >> 1) & 15) << 8);
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return 1;
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}
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static inline int in_range(void *addr, void *base)
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{
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int diff = (uintptr_t)addr - (uintptr_t)base;
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if (diff < -4095 || diff > 4095)
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return 0;
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return 1;
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}
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void host_arm_ADD_REG_LSL(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift);
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void host_arm_AND_REG_LSL(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift);
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void host_arm_EOR_REG_LSL(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift);
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void host_arm_ORR_REG_LSL(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift);
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void host_arm_SUB_REG_LSL(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift);
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void host_arm_ADD_IMM(codeblock_t *block, int dst_reg, int src_reg, uint32_t imm)
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{
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uint32_t arm_imm;
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if ((int32_t)imm < 0 && imm != 0x80000000)
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{
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host_arm_SUB_IMM(block, dst_reg, src_reg, -(int32_t)imm);
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}
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else if (get_arm_imm(imm, &arm_imm))
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{
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codegen_addlong(block, COND_AL | OPCODE_ADD_IMM | Rd(dst_reg) | Rn(src_reg) | arm_imm);
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}
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else
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{
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int offset = add_literal(block, imm);
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host_arm_LDR_IMM(block, REG_TEMP, REG_LITERAL, offset);
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host_arm_ADD_REG_LSL(block, dst_reg, src_reg, REG_TEMP, 0);
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}
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}
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void host_arm_ADD_REG_LSL(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift)
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{
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codegen_addlong(block, COND_AL | OPCODE_ADD_REG | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m) | SHIFT_LSL_IMM(shift));
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}
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void host_arm_AND_IMM(codeblock_t *block, int dst_reg, int src_reg, uint32_t imm)
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{
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uint32_t arm_imm;
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if (get_arm_imm(imm, &arm_imm))
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{
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codegen_addlong(block, COND_AL | OPCODE_AND_IMM | Rd(dst_reg) | Rn(src_reg) | arm_imm);
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}
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else if (get_arm_imm(~imm, &arm_imm))
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{
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codegen_addlong(block, COND_AL | OPCODE_BIC_IMM | Rd(dst_reg) | Rn(src_reg) | arm_imm);
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}
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else
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{
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int offset = add_literal(block, imm);
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host_arm_LDR_IMM(block, REG_TEMP, REG_LITERAL, offset);
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host_arm_AND_REG_LSL(block, dst_reg, src_reg, REG_TEMP, 0);
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}
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}
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void host_arm_AND_REG_LSL(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift)
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{
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codegen_addlong(block, COND_AL | OPCODE_AND_REG | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m) | SHIFT_LSL_IMM(shift));
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}
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void host_arm_BFI(codeblock_t *block, int dst_reg, int src_reg, int lsb, int width)
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{
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codegen_addlong(block, OPCODE_BFI | Rd(dst_reg) | Rm(src_reg) | BFI_lsb(lsb) | BFI_msb((lsb + width) - 1));
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}
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void host_arm_BIC_REG_LSL(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift)
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{
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codegen_addlong(block, COND_AL | OPCODE_BIC_REG | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m) | SHIFT_LSL_IMM(shift));
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}
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void host_arm_BIC_REG_LSR(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift)
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{
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codegen_addlong(block, COND_AL | OPCODE_BIC_REG | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m) | SHIFT_LSR_IMM(shift));
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}
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void host_arm_BL(codeblock_t *block, uintptr_t dest_addr)
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{
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uint32_t offset = (dest_addr - (uintptr_t)&block->data[block_pos]) - 8;
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if ((offset & 0xfe000000) && (offset & 0xfe000000) != 0xfe000000)
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{
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host_arm_MOV_IMM(block, REG_R3, dest_addr);
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host_arm_BLX(block, REG_R3);
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}
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else
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codegen_addlong(block, COND_AL | OPCODE_BL | B_OFFSET(offset));
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}
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void host_arm_BLX(codeblock_t *block, int addr_reg)
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{
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codegen_addlong(block, OPCODE_BLX | Rm(addr_reg));
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}
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uint32_t *host_arm_BEQ_(codeblock_t *block)
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{
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codegen_addlong(block, COND_EQ | OPCODE_B);
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return (uint32_t *)&block->data[block_pos - 4];
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}
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uint32_t *host_arm_BNE_(codeblock_t *block)
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{
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codegen_addlong(block, COND_NE | OPCODE_B);
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return (uint32_t *)&block->data[block_pos - 4];
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}
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void host_arm_BEQ(codeblock_t *block, uintptr_t dest_addr)
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{
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uint32_t offset = (dest_addr - (uintptr_t)&block->data[block_pos]) - 8;
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if ((offset & 0xfe000000) && (offset & 0xfe000000) != 0xfe000000)
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fatal("host_arm_BEQ - out of range %08x %i\n", offset, offset);
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codegen_addlong(block, COND_EQ | OPCODE_B | B_OFFSET(offset));
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}
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void host_arm_BNE(codeblock_t *block, uintptr_t dest_addr)
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{
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uint32_t offset = (dest_addr - (uintptr_t)&block->data[block_pos]) - 8;
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if ((offset & 0xfe000000) && (offset & 0xfe000000) != 0xfe000000)
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fatal("host_arm_BNE - out of range %08x %i\n", offset, offset);
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codegen_addlong(block, COND_NE | OPCODE_B | B_OFFSET(offset));
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}
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void host_arm_CMN_IMM(codeblock_t *block, int src_reg, uint32_t imm)
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{
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uint32_t arm_imm;
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if ((int32_t)imm < 0 && imm != 0x80000000)
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{
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host_arm_CMP_IMM(block, src_reg, -(int32_t)imm);
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}
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else if (get_arm_imm(imm, &arm_imm))
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{
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codegen_addlong(block, COND_AL | OPCODE_CMN_IMM | Rn(src_reg) | arm_imm);
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}
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else
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{
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int offset = add_literal(block, imm);
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host_arm_LDR_IMM(block, REG_TEMP, REG_LITERAL, offset);
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host_arm_CMN_REG_LSL(block, src_reg, REG_TEMP, 0);
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}
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}
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void host_arm_CMN_REG_LSL(codeblock_t *block, int src_reg_n, int src_reg_m, int shift)
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{
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codegen_addlong(block, COND_AL | OPCODE_CMN_REG | Rn(src_reg_n) | Rm(src_reg_m) | SHIFT_LSL_IMM(shift));
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}
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void host_arm_CMP_IMM(codeblock_t *block, int src_reg, uint32_t imm)
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{
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uint32_t arm_imm;
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if ((int32_t)imm < 0 && imm != 0x80000000)
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{
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host_arm_CMN_IMM(block, src_reg, -(int32_t)imm);
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}
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else if (get_arm_imm(imm, &arm_imm))
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{
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codegen_addlong(block, COND_AL | OPCODE_CMP_IMM | Rn(src_reg) | arm_imm);
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}
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else
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{
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int offset = add_literal(block, imm);
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host_arm_LDR_IMM(block, REG_TEMP, REG_LITERAL, offset);
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host_arm_CMP_REG_LSL(block, src_reg, REG_TEMP, 0);
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}
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}
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void host_arm_CMP_REG_LSL(codeblock_t *block, int src_reg_n, int src_reg_m, int shift)
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{
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codegen_addlong(block, COND_AL | OPCODE_CMP_REG | Rn(src_reg_n) | Rm(src_reg_m) | SHIFT_LSL_IMM(shift));
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}
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void host_arm_EOR_IMM(codeblock_t *block, int dst_reg, int src_reg, uint32_t imm)
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{
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uint32_t arm_imm;
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if (get_arm_imm(imm, &arm_imm))
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{
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codegen_addlong(block, COND_AL | OPCODE_EOR_IMM | Rd(dst_reg) | Rn(src_reg) | arm_imm);
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}
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else
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{
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int offset = add_literal(block, imm);
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host_arm_LDR_IMM(block, REG_TEMP, REG_LITERAL, offset);
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host_arm_EOR_REG_LSL(block, dst_reg, src_reg, REG_TEMP, 0);
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}
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}
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void host_arm_EOR_REG_LSL(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift)
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{
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codegen_addlong(block, COND_AL | OPCODE_EOR_REG | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m) | SHIFT_LSL_IMM(shift));
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}
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void host_arm_LDMIA_WB(codeblock_t *block, int addr_reg, uint32_t reg_mask)
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{
|
||||
codegen_addlong(block, COND_AL | OPCODE_LDMIA_WB | Rn(addr_reg) | reg_mask);
|
||||
}
|
||||
|
||||
void host_arm_LDR_IMM(codeblock_t *block, int dst_reg, int addr_reg, int offset)
|
||||
{
|
||||
codegen_addlong(block, COND_AL | OPCODE_LDR_IMM | Rn(addr_reg) | Rd(dst_reg) | arm_data_offset(offset));
|
||||
}
|
||||
void host_arm_LDR_IMM_POST(codeblock_t *block, int dst_reg, int addr_reg, int offset)
|
||||
{
|
||||
codegen_addlong(block, COND_AL | OPCODE_LDR_IMM_POST | Rn(addr_reg) | Rd(dst_reg) | arm_data_offset(offset));
|
||||
}
|
||||
void host_arm_LDR_REG_LSL(codeblock_t *block, int dst_reg, int addr_reg, int offset_reg, int shift)
|
||||
{
|
||||
codegen_addlong(block, COND_AL | OPCODE_LDR_REG | Rn(addr_reg) | Rd(dst_reg) | Rm(offset_reg) | SHIFT_LSL_IMM(shift));
|
||||
}
|
||||
|
||||
void host_arm_LDRB_ABS(codeblock_t *block, int dst_reg, void *p)
|
||||
{
|
||||
if (in_range(p, &cpu_state))
|
||||
host_arm_LDRB_IMM(block, dst_reg, REG_CPUSTATE, (uintptr_t)p - (uintptr_t)&cpu_state);
|
||||
else
|
||||
fatal("LDRB_ABS - not in range\n");
|
||||
}
|
||||
void host_arm_LDRB_IMM(codeblock_t *block, int dst_reg, int addr_reg, int offset)
|
||||
{
|
||||
codegen_addlong(block, COND_AL | OPCODE_LDRB_IMM | Rn(addr_reg) | Rd(dst_reg) | arm_data_offset(offset));
|
||||
}
|
||||
void host_arm_LDRB_REG_LSL(codeblock_t *block, int dst_reg, int addr_reg, int offset_reg, int shift)
|
||||
{
|
||||
codegen_addlong(block, COND_AL | OPCODE_LDRB_REG | Rn(addr_reg) | Rd(dst_reg) | Rm(offset_reg) | SHIFT_LSL_IMM(shift));
|
||||
}
|
||||
|
||||
void host_arm_LDRH_REG(codeblock_t *block, int dst_reg, int addr_reg, int offset_reg)
|
||||
{
|
||||
codegen_addlong(block, COND_AL | OPCODE_LDRH_REG | Rn(addr_reg) | Rd(dst_reg) | Rm(offset_reg));
|
||||
}
|
||||
|
||||
void host_arm_MOV_IMM(codeblock_t *block, int dst_reg, uint32_t imm)
|
||||
{
|
||||
uint32_t arm_imm;
|
||||
|
||||
if (get_arm_imm(imm, &arm_imm))
|
||||
{
|
||||
codegen_addlong(block, COND_AL | OPCODE_MOV_IMM | Rd(dst_reg) | arm_imm);
|
||||
}
|
||||
else
|
||||
{
|
||||
host_arm_MOVW_IMM(block, dst_reg, imm & 0xffff);
|
||||
if (imm >> 16)
|
||||
host_arm_MOVT_IMM(block, dst_reg, imm >> 16);
|
||||
}
|
||||
}
|
||||
|
||||
void host_arm_MOV_REG_LSL(codeblock_t *block, int dst_reg, int src_reg, int shift)
|
||||
{
|
||||
codegen_addlong(block, COND_AL | OPCODE_MOV_REG | Rd(dst_reg) | Rm(src_reg) | SHIFT_LSL_IMM(shift));
|
||||
}
|
||||
void host_arm_MOV_REG_LSR(codeblock_t *block, int dst_reg, int src_reg, int shift)
|
||||
{
|
||||
codegen_addlong(block, COND_AL | OPCODE_MOV_REG | Rd(dst_reg) | Rm(src_reg) | SHIFT_LSR_IMM(shift));
|
||||
}
|
||||
|
||||
void host_arm_MOVT_IMM(codeblock_t *block, int dst_reg, uint16_t imm)
|
||||
{
|
||||
codegen_addlong(block, COND_AL | OPCODE_MOVT_IMM | Rd(dst_reg) | MOVT_IMM(imm));
|
||||
}
|
||||
void host_arm_MOVW_IMM(codeblock_t *block, int dst_reg, uint16_t imm)
|
||||
{
|
||||
codegen_addlong(block, COND_AL | OPCODE_MOVW_IMM | Rd(dst_reg) | MOVW_IMM(imm));
|
||||
}
|
||||
|
||||
void host_arm_MVN_REG_LSL(codeblock_t *block, int dst_reg, int src_reg, int shift)
|
||||
{
|
||||
codegen_addlong(block, COND_AL | OPCODE_MVN_REG | Rd(dst_reg) | Rm(src_reg) | SHIFT_LSL_IMM(shift));
|
||||
}
|
||||
|
||||
void host_arm_ORR_IMM(codeblock_t *block, int dst_reg, int src_reg, uint32_t imm)
|
||||
{
|
||||
uint32_t arm_imm;
|
||||
|
||||
if (get_arm_imm(imm, &arm_imm))
|
||||
{
|
||||
codegen_addlong(block, COND_AL | OPCODE_ORR_IMM | Rd(dst_reg) | Rn(src_reg) | arm_imm);
|
||||
}
|
||||
else
|
||||
{
|
||||
int offset = add_literal(block, imm);
|
||||
host_arm_LDR_IMM(block, REG_TEMP, REG_LITERAL, offset);
|
||||
host_arm_ORR_REG_LSL(block, dst_reg, src_reg, REG_TEMP, 0);
|
||||
}
|
||||
}
|
||||
|
||||
void host_arm_ORR_REG_LSL(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift)
|
||||
{
|
||||
codegen_addlong(block, COND_AL | OPCODE_ORR_REG | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m) | SHIFT_LSL_IMM(shift));
|
||||
}
|
||||
|
||||
void host_arm_RSB_REG_LSR(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift)
|
||||
{
|
||||
codegen_addlong(block, COND_AL | OPCODE_RSB_REG | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m) | SHIFT_LSR_IMM(shift));
|
||||
}
|
||||
|
||||
void host_arm_STMDB_WB(codeblock_t *block, int addr_reg, uint32_t reg_mask)
|
||||
{
|
||||
codegen_addlong(block, COND_AL | OPCODE_STMDB_WB | Rn(addr_reg) | reg_mask);
|
||||
}
|
||||
|
||||
void host_arm_STR_IMM(codeblock_t *block, int src_reg, int addr_reg, int offset)
|
||||
{
|
||||
codegen_addlong(block, COND_AL | OPCODE_STR_IMM | Rn(addr_reg) | Rd(src_reg) | arm_data_offset(offset));
|
||||
}
|
||||
void host_arm_STR_IMM_WB(codeblock_t *block, int src_reg, int addr_reg, int offset)
|
||||
{
|
||||
codegen_addlong(block, COND_AL | OPCODE_STR_IMM_WB | Rn(addr_reg) | Rd(src_reg) | arm_data_offset(offset));
|
||||
}
|
||||
void host_arm_STR_REG_LSL(codeblock_t *block, int src_reg, int addr_reg, int offset_reg, int shift)
|
||||
{
|
||||
codegen_addlong(block, COND_AL | OPCODE_STR_REG | Rn(addr_reg) | Rd(src_reg) | Rm(offset_reg) | SHIFT_LSL_IMM(shift));
|
||||
}
|
||||
|
||||
void host_arm_STRB_IMM(codeblock_t *block, int src_reg, int addr_reg, int offset)
|
||||
{
|
||||
codegen_addlong(block, COND_AL | OPCODE_STRB_IMM | Rn(addr_reg) | Rd(src_reg) | arm_data_offset(offset));
|
||||
}
|
||||
void host_arm_STRB_REG_LSL(codeblock_t *block, int src_reg, int addr_reg, int offset_reg, int shift)
|
||||
{
|
||||
codegen_addlong(block, COND_AL | OPCODE_STRB_REG | Rn(addr_reg) | Rd(src_reg) | Rm(offset_reg) | SHIFT_LSL_IMM(shift));
|
||||
}
|
||||
|
||||
void host_arm_STRH_REG(codeblock_t *block, int src_reg, int addr_reg, int offset_reg)
|
||||
{
|
||||
codegen_addlong(block, COND_AL | OPCODE_STRH_REG | Rn(addr_reg) | Rd(src_reg) | Rm(offset_reg));
|
||||
}
|
||||
|
||||
void host_arm_SUB_IMM(codeblock_t *block, int dst_reg, int src_reg, uint32_t imm)
|
||||
{
|
||||
uint32_t arm_imm;
|
||||
|
||||
if ((int32_t)imm < 0 && imm != 0x80000000)
|
||||
{
|
||||
host_arm_ADD_IMM(block, dst_reg, src_reg, -(int32_t)imm);
|
||||
}
|
||||
else if (get_arm_imm(imm, &arm_imm))
|
||||
{
|
||||
codegen_addlong(block, COND_AL | OPCODE_SUB_IMM | Rd(dst_reg) | Rn(src_reg) | arm_imm);
|
||||
}
|
||||
else
|
||||
{
|
||||
int offset = add_literal(block, imm);
|
||||
host_arm_LDR_IMM(block, REG_TEMP, REG_LITERAL, offset);
|
||||
host_arm_SUB_REG_LSL(block, dst_reg, src_reg, REG_TEMP, 0);
|
||||
}
|
||||
}
|
||||
|
||||
void host_arm_SUB_REG_LSL(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift)
|
||||
{
|
||||
codegen_addlong(block, COND_AL | OPCODE_SUB_REG | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m) | SHIFT_LSL_IMM(shift));
|
||||
}
|
||||
void host_arm_SUB_REG_LSR(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift)
|
||||
{
|
||||
codegen_addlong(block, COND_AL | OPCODE_SUB_REG | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m) | SHIFT_LSR_IMM(shift));
|
||||
}
|
||||
|
||||
void host_arm_TST_IMM(codeblock_t *block, int src_reg, uint32_t imm)
|
||||
{
|
||||
uint32_t arm_imm;
|
||||
|
||||
if (get_arm_imm(imm, &arm_imm))
|
||||
{
|
||||
codegen_addlong(block, COND_AL | OPCODE_TST_IMM | Rn(src_reg) | arm_imm);
|
||||
}
|
||||
else
|
||||
{
|
||||
int offset = add_literal(block, imm);
|
||||
host_arm_LDR_IMM(block, REG_TEMP, REG_LITERAL, offset);
|
||||
host_arm_TST_REG(block, src_reg, REG_TEMP);
|
||||
}
|
||||
}
|
||||
void host_arm_TST_REG(codeblock_t *block, int src_reg1, int src_reg2)
|
||||
{
|
||||
codegen_addlong(block, COND_AL | OPCODE_TST_REG | Rn(src_reg1) | Rm(src_reg2));
|
||||
}
|
||||
|
||||
void host_arm_UADD8(codeblock_t *block, int dst_reg, int src_reg_a, int src_reg_b)
|
||||
{
|
||||
codegen_addlong(block, COND_AL | OPCODE_UADD8 | Rd(dst_reg) | Rn(src_reg_a) | Rm(src_reg_b));
|
||||
}
|
||||
|
||||
void host_arm_UADD16(codeblock_t *block, int dst_reg, int src_reg_a, int src_reg_b)
|
||||
{
|
||||
codegen_addlong(block, COND_AL | OPCODE_UADD16 | Rd(dst_reg) | Rn(src_reg_a) | Rm(src_reg_b));
|
||||
}
|
||||
|
||||
void host_arm_USUB8(codeblock_t *block, int dst_reg, int src_reg_a, int src_reg_b)
|
||||
{
|
||||
codegen_addlong(block, COND_AL | OPCODE_USUB8 | Rd(dst_reg) | Rn(src_reg_a) | Rm(src_reg_b));
|
||||
}
|
||||
|
||||
void host_arm_USUB16(codeblock_t *block, int dst_reg, int src_reg_a, int src_reg_b)
|
||||
{
|
||||
codegen_addlong(block, COND_AL | OPCODE_USUB16 | Rd(dst_reg) | Rn(src_reg_a) | Rm(src_reg_b));
|
||||
}
|
||||
|
||||
void host_arm_UXTB(codeblock_t *block, int dst_reg, int src_reg, int rotate)
|
||||
{
|
||||
codegen_addlong(block, OPCODE_UXTB | Rd(dst_reg) | Rm(src_reg) | UXTB_ROTATE(rotate));
|
||||
}
|
||||
|
||||
void host_arm_UXTH(codeblock_t *block, int dst_reg, int src_reg, int rotate)
|
||||
{
|
||||
codegen_addlong(block, OPCODE_UXTH | Rd(dst_reg) | Rm(src_reg) | UXTB_ROTATE(rotate));
|
||||
}
|
||||
|
||||
#endif
|
||||
Loading…
Reference in a new issue