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Add recompiled versions of mem->reg, reg->mem and imm->mem versions of MOV.

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This commit is contained in:
SarahW 2018-07-25 20:16:58 +01:00
commit f27b7f757a
30 changed files with 5225 additions and 2160 deletions
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144
src/codegen_backend_arm.c
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@ -5,6 +5,7 @@
#include "codegen.h"
#include "codegen_backend.h"
#include "codegen_backend_arm_defs.h"
#include "codegen_backend_arm_ops.h"
#include "x86.h"
#if defined(__linux__) || defined(__APPLE__)
@ -15,6 +16,14 @@
#include <windows.h>
#endif
void *codegen_mem_load_byte;
void *codegen_mem_load_word;
void *codegen_mem_load_long;
void *codegen_mem_store_byte;
void *codegen_mem_store_word;
void *codegen_mem_store_long;
int codegen_host_reg_list[CODEGEN_HOST_REGS] =
{
REG_R4,
@ -22,6 +31,137 @@ int codegen_host_reg_list[CODEGEN_HOST_REGS] =
REG_R6,
};
static void build_load_routine(codeblock_t *block, int size)
{
uint32_t *branch_offset;
uint8_t *misaligned_offset;
/*In - R0 = address
Out - R0 = data, R1 = abrt*/
/*MOV R1, R0, LSR #12
MOV R2, #readlookup2
LDR R1, [R2, R1, LSL #2]
CMP R1, #-1
BNE +
LDRB R0, [R1, R0]
MOV R1, #0
MOV PC, LR
* STR LR, [SP, -4]!
BL readmemb386l
LDRB R1, cpu_state.abrt
LDR PC, [SP], #4
*/
host_arm_MOV_REG_LSR(block, REG_R1, REG_R0, 12);
host_arm_MOV_IMM(block, REG_R2, (uint32_t)readlookup2);
host_arm_LDR_REG_LSL(block, REG_R1, REG_R2, REG_R1, 2);
if (size != 1)
{
host_arm_TST_IMM(block, REG_R0, size-1);
misaligned_offset = host_arm_BNE_(block);
}
host_arm_CMP_IMM(block, REG_R1, -1);
branch_offset = host_arm_BEQ_(block);
if (size == 1)
host_arm_LDRB_REG(block, REG_R0, REG_R1, REG_R0);
else if (size == 2)
host_arm_LDRH_REG(block, REG_R0, REG_R1, REG_R0);
else if (size == 4)
host_arm_LDR_REG(block, REG_R0, REG_R1, REG_R0);
host_arm_MOV_IMM(block, REG_R1, 0);
host_arm_MOV_REG(block, REG_PC, REG_LR);
*branch_offset |= ((((uintptr_t)&block->data[block_pos] - (uintptr_t)branch_offset) - 8) & 0x3fffffc) >> 2;
if (size != 1)
*misaligned_offset |= ((((uintptr_t)&block->data[block_pos] - (uintptr_t)misaligned_offset) - 8) & 0x3fffffc) >> 2;
host_arm_STR_IMM_WB(block, REG_LR, REG_SP, -4);
if (size == 1)
host_arm_BL(block, (uintptr_t)readmemb386l);
else if (size == 2)
host_arm_BL(block, (uintptr_t)readmemwl);
else if (size == 4)
host_arm_BL(block, (uintptr_t)readmemll);
else
fatal("build_load_routine - unknown size %i\n", size);
host_arm_LDRB_ABS(block, REG_R1, &cpu_state.abrt);
host_arm_LDR_IMM_POST(block, REG_PC, REG_SP, 4);
block_pos = (block_pos + 63) & ~63;
}
static void build_store_routine(codeblock_t *block, int size)
{
uint8_t *branch_offset;
uint8_t *misaligned_offset;
/*In - R0 = address
Out - R0 = data, R1 = abrt*/
/*MOV R1, R0, LSR #12
MOV R2, #readlookup2
LDR R1, [R2, R1, LSL #2]
CMP R1, #-1
BNE +
LDRB R0, [R1, R0]
MOV R1, #0
MOV PC, LR
* STR LR, [SP, -4]!
BL readmemb386l
LDRB R1, cpu_state.abrt
LDR PC, [SP], #4
*/
host_arm_MOV_REG_LSR(block, REG_R2, REG_R0, 12);
host_arm_MOV_IMM(block, REG_R3, (uint32_t)writelookup2);
host_arm_LDR_REG_LSL(block, REG_R2, REG_R3, REG_R2, 2);
if (size != 1)
{
host_arm_TST_IMM(block, REG_R0, size-1);
misaligned_offset = host_arm_BNE_(block);
}
host_arm_CMP_IMM(block, REG_R2, -1);
branch_offset = host_arm_BEQ_(block);
if (size == 1)
host_arm_STRB_REG(block, REG_R1, REG_R2, REG_R0);
else if (size == 2)
host_arm_STRH_REG(block, REG_R1, REG_R2, REG_R0);
else if (size == 4)
host_arm_STR_REG(block, REG_R1, REG_R2, REG_R0);
host_arm_MOV_IMM(block, REG_R1, 0);
host_arm_MOV_REG(block, REG_PC, REG_LR);
*branch_offset |= ((((uintptr_t)&block->data[block_pos] - (uintptr_t)branch_offset) - 8) & 0x3fffffc) >> 2;
if (size != 1)
*misaligned_offset |= ((((uintptr_t)&block->data[block_pos] - (uintptr_t)misaligned_offset) - 8) & 0x3fffffc) >> 2;
host_arm_STR_IMM_WB(block, REG_LR, REG_SP, -4);
if (size == 1)
host_arm_BL(block, (uintptr_t)writememb386l);
else if (size == 2)
host_arm_BL(block, (uintptr_t)writememwl);
else if (size == 4)
host_arm_BL(block, (uintptr_t)writememll);
else
fatal("build_store_routine - unknown size %i\n", size);
host_arm_LDRB_ABS(block, REG_R1, &cpu_state.abrt);
host_arm_LDR_IMM_POST(block, REG_PC, REG_SP, 4);
block_pos = (block_pos + 63) & ~63;
}
static void build_loadstore_routines(codeblock_t *block)
{
codegen_mem_load_byte = &codeblock[block_current].data[block_pos];
build_load_routine(block, 1);
codegen_mem_load_word = &codeblock[block_current].data[block_pos];
build_load_routine(block, 2);
codegen_mem_load_long = &codeblock[block_current].data[block_pos];
build_load_routine(block, 4);
codegen_mem_store_byte = &codeblock[block_current].data[block_pos];
build_store_routine(block, 1);
codegen_mem_store_word = &codeblock[block_current].data[block_pos];
build_store_routine(block, 2);
codegen_mem_store_long = &codeblock[block_current].data[block_pos];
build_store_routine(block, 4);
}
void codegen_backend_init()
{
int c;
@ -57,6 +197,10 @@ void codegen_backend_init()
}
#endif
// pclog("Codegen is %p\n", (void *)pages[0xfab12 >> 12].block);
block_current = BLOCK_SIZE;
block_pos = 0;
build_loadstore_routines(&codeblock[block_current]);
}
/*R11 - literal pool