Moved more variables into cpu_state structure.
This commit is contained in:
SarahW
parent
c664682758
commit
eb126fd822
50 changed files with 1454 additions and 1481 deletions
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@ -5,13 +5,13 @@ static int opARPL_a16(uint32_t fetchdat)
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NOTRM
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fetch_ea_16(fetchdat);
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pclog("ARPL_a16\n");
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temp_seg = geteaw(); if (abrt) return 1;
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temp_seg = geteaw(); if (cpu_state.abrt) return 1;
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flags_rebuild();
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if ((temp_seg & 3) < (cpu_state.regs[cpu_reg].w & 3))
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{
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temp_seg = (temp_seg & 0xfffc) | (cpu_state.regs[cpu_reg].w & 3);
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seteaw(temp_seg); if (abrt) return 1;
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seteaw(temp_seg); if (cpu_state.abrt) return 1;
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flags |= Z_FLAG;
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}
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else
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@ -27,13 +27,13 @@ static int opARPL_a32(uint32_t fetchdat)
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NOTRM
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fetch_ea_32(fetchdat);
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pclog("ARPL_a32\n");
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temp_seg = geteaw(); if (abrt) return 1;
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temp_seg = geteaw(); if (cpu_state.abrt) return 1;
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flags_rebuild();
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if ((temp_seg & 3) < (cpu_state.regs[cpu_reg].w & 3))
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{
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temp_seg = (temp_seg & 0xfffc) | (cpu_state.regs[cpu_reg].w & 3);
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seteaw(temp_seg); if (abrt) return 1;
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seteaw(temp_seg); if (cpu_state.abrt) return 1;
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flags |= Z_FLAG;
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}
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else
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@ -52,7 +52,7 @@ static int opARPL_a32(uint32_t fetchdat)
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NOTRM \
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fetch_ea(fetchdat); \
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\
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sel = geteaw(); if (abrt) return 1; \
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sel = geteaw(); if (cpu_state.abrt) return 1; \
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\
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flags_rebuild(); \
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if (!(sel & 0xfffc)) { flags &= ~Z_FLAG; return 0; } /*Null selector*/ \
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@ -61,7 +61,7 @@ static int opARPL_a32(uint32_t fetchdat)
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{ \
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cpl_override = 1; \
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desc = readmemw(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 4); \
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cpl_override = 0; if (abrt) return 1; \
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cpl_override = 0; if (cpu_state.abrt) return 1; \
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} \
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flags &= ~Z_FLAG; \
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if ((desc & 0x1f00) == 0x000) valid = 0; \
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@ -84,7 +84,7 @@ static int opARPL_a32(uint32_t fetchdat)
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cpl_override = 0; \
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} \
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CLOCK_CYCLES(11); \
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return abrt; \
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return cpu_state.abrt; \
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}
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opLAR(w_a16, fetch_ea_16, 0)
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@ -101,7 +101,7 @@ opLAR(l_a32, fetch_ea_32, 1)
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NOTRM \
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fetch_ea(fetchdat); \
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\
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sel = geteaw(); if (abrt) return 1; \
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sel = geteaw(); if (cpu_state.abrt) return 1; \
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flags_rebuild(); \
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flags &= ~Z_FLAG; \
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if (!(sel & 0xfffc)) return 0; /*Null selector*/ \
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@ -110,7 +110,7 @@ opLAR(l_a32, fetch_ea_32, 1)
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{ \
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cpl_override = 1; \
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desc = readmemw(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 4); \
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cpl_override = 0; if (abrt) return 1; \
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cpl_override = 0; if (cpu_state.abrt) return 1; \
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} \
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if ((desc & 0x1400) == 0x400) valid = 0; /*Interrupt or trap or call gate*/ \
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if ((desc & 0x1f00) == 0x000) valid = 0; /*Invalid*/ \
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@ -139,7 +139,7 @@ opLAR(l_a32, fetch_ea_32, 1)
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cpl_override = 0; \
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} \
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CLOCK_CYCLES(10); \
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return abrt; \
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return cpu_state.abrt; \
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}
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opLSL(w_a16, fetch_ea_16, 0)
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@ -173,13 +173,13 @@ static int op0F00_common(uint32_t fetchdat)
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x86gpf(NULL,0);
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return 1;
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}
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sel = geteaw(); if (abrt) return 1;
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sel = geteaw(); if (cpu_state.abrt) return 1;
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addr = (sel & ~7) + gdt.base;
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limit = readmemw(0, addr) + ((readmemb(0, addr + 6) & 0xf) << 16);
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base = (readmemw(0, addr + 2)) | (readmemb(0, addr + 4) << 16) | (readmemb(0, addr + 7) << 24);
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access = readmemb(0, addr + 5);
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granularity = readmemb(0, addr + 6) & 0x80;
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if (abrt) return 1;
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if (cpu_state.abrt) return 1;
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ldt.limit = limit;
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ldt.access = access;
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if (granularity)
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@ -198,13 +198,13 @@ static int op0F00_common(uint32_t fetchdat)
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x86gpf(NULL,0);
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break;
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}
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sel = geteaw(); if (abrt) return 1;
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sel = geteaw(); if (cpu_state.abrt) return 1;
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addr = (sel & ~7) + gdt.base;
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limit = readmemw(0, addr) + ((readmemb(0, addr + 6) & 0xf) << 16);
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base = (readmemw(0, addr + 2)) | (readmemb(0, addr + 4) << 16) | (readmemb(0, addr + 7) << 24);
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access = readmemb(0, addr + 5);
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granularity = readmemb(0, addr + 6) & 0x80;
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if (abrt) return 1;
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if (cpu_state.abrt) return 1;
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tr.seg = sel;
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tr.limit = limit;
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tr.access = access;
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@ -217,14 +217,14 @@ static int op0F00_common(uint32_t fetchdat)
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CLOCK_CYCLES(20);
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break;
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case 0x20: /*VERR*/
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sel = geteaw(); if (abrt) return 1;
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sel = geteaw(); if (cpu_state.abrt) return 1;
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flags_rebuild();
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flags &= ~Z_FLAG;
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if (!(sel & 0xfffc)) return 0; /*Null selector*/
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cpl_override = 1;
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valid = (sel & ~7) < ((sel & 4) ? ldt.limit : gdt.limit);
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desc = readmemw(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 4);
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cpl_override = 0; if (abrt) return 1;
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cpl_override = 0; if (cpu_state.abrt) return 1;
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if (!(desc & 0x1000)) valid = 0;
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if ((desc & 0xC00) != 0xC00) /*Exclude conforming code segments*/
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{
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@ -236,14 +236,14 @@ static int op0F00_common(uint32_t fetchdat)
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CLOCK_CYCLES(20);
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break;
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case 0x28: /*VERW*/
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sel = geteaw(); if (abrt) return 1;
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sel = geteaw(); if (cpu_state.abrt) return 1;
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flags_rebuild();
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flags &= ~Z_FLAG;
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if (!(sel & 0xfffc)) return 0; /*Null selector*/
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cpl_override = 1;
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valid = (sel & ~7) < ((sel & 4) ? ldt.limit : gdt.limit);
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desc = readmemw(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 4);
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cpl_override = 0; if (abrt) return 1;
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cpl_override = 0; if (cpu_state.abrt) return 1;
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if (!(desc & 0x1000)) valid = 0;
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dpl = (desc >> 13) & 3; /*Check permissions*/
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if (dpl < CPL || dpl < (sel & 3)) valid = 0;
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@ -259,7 +259,7 @@ static int op0F00_common(uint32_t fetchdat)
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x86illegal();
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break;
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}
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return abrt;
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return cpu_state.abrt;
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}
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static int op0F00_a16(uint32_t fetchdat)
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@ -311,7 +311,7 @@ static int op0F01_common(uint32_t fetchdat, int is32, int is286)
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}
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// pclog("LGDT %08X:%08X\n", easeg, eaaddr);
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limit = geteaw();
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base = readmeml(0, easeg + cpu_state.eaaddr + 2); if (abrt) return 1;
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base = readmeml(0, easeg + cpu_state.eaaddr + 2); if (cpu_state.abrt) return 1;
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// pclog(" %08X %04X\n", base, limit);
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gdt.limit = limit;
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gdt.base = base;
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@ -327,7 +327,7 @@ static int op0F01_common(uint32_t fetchdat, int is32, int is286)
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}
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// pclog("LIDT %08X:%08X\n", easeg, eaaddr);
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limit = geteaw();
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base = readmeml(0, easeg + cpu_state.eaaddr + 2); if (abrt) return 1;
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base = readmeml(0, easeg + cpu_state.eaaddr + 2); if (cpu_state.abrt) return 1;
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// pclog(" %08X %04X\n", base, limit);
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idt.limit = limit;
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idt.base = base;
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@ -347,7 +347,7 @@ static int op0F01_common(uint32_t fetchdat, int is32, int is286)
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x86gpf(NULL, 0);
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break;
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}
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tempw = geteaw(); if (abrt) return 1;
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tempw = geteaw(); if (cpu_state.abrt) return 1;
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if (msw & 1) tempw |= 1;
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msw = tempw;
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break;
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@ -372,7 +372,7 @@ static int op0F01_common(uint32_t fetchdat, int is32, int is286)
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x86illegal();
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break;
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}
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return abrt;
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return cpu_state.abrt;
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}
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static int op0F01_w_a16(uint32_t fetchdat)
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