From e737d2fa45bafc5bf9ee198f644f097276390034 Mon Sep 17 00:00:00 2001
From: TomW <TomW@localhost>
Date: Sat, 29 Mar 2014 14:28:13 +0000
Subject: [PATCH] Loading a segment register in real mode no longer clears
 USE32. CR3 no longer masks values written to it. Real mode interrupts now
 take IDT base into account. Fixes 'huge unreal' mode (flat assembler).

---
 src/386.c              | 8 ++++----
 src/808x.c             | 2 ++
 src/x86_ops_mov_ctrl.h | 4 ++--
 src/x86seg.c           | 1 -
 4 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/src/386.c b/src/386.c
index eb2b800..32a2ceb 100644
--- a/src/386.c
+++ b/src/386.c
@@ -339,7 +339,7 @@ void x86_int(int num)
                         writememw(ss,((SP-6)&0xFFFF),pc);
                         SP-=6;
                 }
-                addr=num<<2;
+                addr = (num << 2) + idt.base;
 
                 flags&=~I_FLAG;
                 flags&=~T_FLAG;
@@ -376,7 +376,7 @@ void x86_int_sw(int num)
                         writememw(ss,((SP-6)&0xFFFF),pc);
                         SP-=6;
                 }
-                addr=num<<2;
+                addr = (num << 2) + idt.base;
 
                 flags&=~I_FLAG;
                 flags&=~T_FLAG;
@@ -1343,7 +1343,7 @@ opcodestart:
                                 writememw(ss,(SP-4)&0xFFFF,CS);
                                 writememw(ss,(SP-6)&0xFFFF,pc);
                                 SP-=6;
-                                addr=1<<2;
+                                addr = (1 << 2) + idt.base;
                                 flags&=~I_FLAG;
                                 flags&=~T_FLAG;
                                 pc=readmemw(0,addr);
@@ -1378,7 +1378,7 @@ opcodestart:
                                         writememw(ss,(SP-4)&0xFFFF,CS);
                                         writememw(ss,(SP-6)&0xFFFF,pc);
                                         SP-=6;
-                                        addr=temp<<2;
+                                        addr = (temp << 2) + idt.base;
                                         flags&=~I_FLAG;
                                         flags&=~T_FLAG;
                                         oxpc=pc;
diff --git a/src/808x.c b/src/808x.c
index 1848b4b..adb1beb 100644
--- a/src/808x.c
+++ b/src/808x.c
@@ -639,6 +639,7 @@ void resetx86()
         cgate32=0;
         loadcs(0xFFFF);
         rammask=0xFFFFFFFF;
+        idt.base = 0;
         flags=2;
         makeznptable();
         initmmucache();
@@ -669,6 +670,7 @@ void softresetx86()
         loadcs(0xFFFF);
         //rammask=0xFFFFFFFF;
         flags=2;
+        idt.base = 0;
 }
 
 static void setznp8(uint8_t val)
diff --git a/src/x86_ops_mov_ctrl.h b/src/x86_ops_mov_ctrl.h
index e227108..e95dc5e 100644
--- a/src/x86_ops_mov_ctrl.h
+++ b/src/x86_ops_mov_ctrl.h
@@ -107,7 +107,7 @@ static int opMOV_CRx_r_a16(uint32_t fetchdat)
                 cr2 = regs[rm].l;
                 break;
                 case 3:
-                cr3 = regs[rm].l & ~0xfff;
+                cr3 = regs[rm].l;
                 flushmmucache();
                 break;
                 default:
@@ -140,7 +140,7 @@ static int opMOV_CRx_r_a32(uint32_t fetchdat)
                 cr2 = regs[rm].l;
                 break;
                 case 3:
-                cr3 = regs[rm].l & ~0xfff;
+                cr3 = regs[rm].l;
                 flushmmucache();
                 break;
                 default:
diff --git a/src/x86seg.c b/src/x86seg.c
index 8665961..b9f5190 100644
--- a/src/x86seg.c
+++ b/src/x86seg.c
@@ -308,7 +308,6 @@ void loadseg(uint16_t seg, x86seg *s)
                 s->seg=seg;
                 if (eflags&VM_FLAG) s->access=3<<5;
                 else                s->access=0<<5;
-                use32=0;
                 if (s==&_ss) stack32=0;
 /*                if (s==&_ds)
                 {