Tweaked 6x86 timings.
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1 changed files with 2 additions and 12 deletions
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@ -24,22 +24,12 @@
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/*Instruction lasts given number of cycles. Does not pair*/
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#define CYCLES(c) (c)
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static int pair_timings[4][4] =
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{
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/* Reg RM RMW Branch*/
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/*Reg*/ {1, 1, 2, 1},
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/*RM*/ {1, 1, 2, 1},
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/*RMW*/ {2, 2, 3, 2},
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/*Branch*/ {-1, -1, -1, -1}
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};
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/*Instruction follows either register timing, read-modify, or read-modify-write.
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May be pairable*/
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#define CYCLES_REG (1 << 0)
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#define CYCLES_RM (1 << 0)
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#define CYCLES_RMW (2 << 0)
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#define CYCLES_BRANCH (2 << 0)
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#define CYCLES_RMW (1 << 0)
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#define CYCLES_BRANCH (1 << 0)
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#define CYCLES_MASK ((1 << 7) - 1)
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