Pentium timing improvements - decoder & pairing limitations on instructions with immediate & displacement, 7 byte limitation on Pentium MMX decoding.
This commit is contained in:
SarahW
parent
182d22cb95
commit
dac7f3406c
1 changed files with 155 additions and 31 deletions
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@ -42,6 +42,11 @@ static int pair_timings[4][4] =
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#define CYCLES_RMW (2 << 0)
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#define CYCLES_BRANCH (3 << 0)
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/*Instruction has immediate data. Can only be used with PAIR_U/PAIR_V/PAIR_UV*/
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#define CYCLES_HASIMM (3 << 2)
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#define CYCLES_IMM8 (1 << 2)
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#define CYCLES_IMM1632 (2 << 2)
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#define CYCLES_MASK ((1 << 7) - 1)
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/*Instruction is MMX shift or pack/unpack instruction*/
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@ -62,6 +67,8 @@ static int pair_timings[4][4] =
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/*Instruction is FXCH and only pairs in V pipe with FX pairable instruction*/
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#define PAIR_FXCH (6 << 29)
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#define PAIR_FPU (4 << 29)
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#define PAIR_MASK (7 << 29)
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/*Instruction has input dependency on register in REG field*/
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@ -296,38 +303,38 @@ static uint32_t opcode_timings_mod3[256] =
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/* ADD ADD ADD ADD*/
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/*00*/ PAIR_UV | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_UV | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_UV | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_UV | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG,
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/* ADD ADD PUSH ES POP ES*/
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PAIR_UV | CYCLES_REG | SRCDEP_EAX | SRCDEP_RM | DSTDEP_EAX, PAIR_UV | CYCLES_REG | SRCDEP_EAX | SRCDEP_RM | DSTDEP_EAX, PAIR_NP | CYCLES(1), PAIR_NP | CYCLES(3),
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PAIR_UV | CYCLES_REG | SRCDEP_EAX | DSTDEP_EAX, PAIR_UV | CYCLES_REG | SRCDEP_EAX | DSTDEP_EAX, PAIR_NP | CYCLES(1), PAIR_NP | CYCLES(3),
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/* OR OR OR OR*/
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PAIR_UV | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_UV | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_UV | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_UV | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG,
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/* OR OR PUSH CS */
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PAIR_UV | CYCLES_REG | SRCDEP_EAX | SRCDEP_RM | DSTDEP_EAX, PAIR_UV | CYCLES_REG | SRCDEP_EAX | SRCDEP_RM | DSTDEP_EAX, PAIR_NP | CYCLES(1), INVALID,
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PAIR_UV | CYCLES_REG | SRCDEP_EAX | DSTDEP_EAX, PAIR_UV | CYCLES_REG | SRCDEP_EAX | DSTDEP_EAX, PAIR_NP | CYCLES(1), INVALID,
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/* ADC ADC ADC ADC*/
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/*10*/ PAIR_U | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_U | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_U | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_U | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG,
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/* ADC ADC PUSH SS POP SS*/
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PAIR_U | CYCLES_REG | SRCDEP_EAX | SRCDEP_RM | DSTDEP_EAX, PAIR_U | CYCLES_REG | SRCDEP_EAX | SRCDEP_RM | DSTDEP_EAX, PAIR_NP | CYCLES(1), PAIR_NP | CYCLES(3),
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PAIR_U | CYCLES_REG | SRCDEP_EAX | DSTDEP_EAX, PAIR_U | CYCLES_REG | SRCDEP_EAX | DSTDEP_EAX, PAIR_NP | CYCLES(1), PAIR_NP | CYCLES(3),
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/* SBB SBB SBB SBB*/
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PAIR_U | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_U | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_U | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_U | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG,
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/* SBB SBB PUSH DS POP DS*/
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PAIR_U | CYCLES_REG | SRCDEP_EAX | SRCDEP_RM | DSTDEP_EAX, PAIR_U | CYCLES_REG | SRCDEP_EAX | SRCDEP_RM | DSTDEP_EAX, PAIR_NP | CYCLES(1), PAIR_NP | CYCLES(3),
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PAIR_U | CYCLES_REG | SRCDEP_EAX | DSTDEP_EAX, PAIR_U | CYCLES_REG | SRCDEP_EAX | DSTDEP_EAX, PAIR_NP | CYCLES(1), PAIR_NP | CYCLES(3),
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/* AND AND AND AND*/
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/*20*/ PAIR_UV | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_UV | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_UV | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_UV | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG,
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/* AND AND DAA*/
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PAIR_UV | CYCLES_REG | SRCDEP_EAX | SRCDEP_RM | DSTDEP_EAX, PAIR_UV | CYCLES_REG | SRCDEP_EAX | SRCDEP_RM | DSTDEP_EAX, INVALID, PAIR_NP | CYCLES(3),
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PAIR_UV | CYCLES_REG | SRCDEP_EAX | DSTDEP_EAX, PAIR_UV | CYCLES_REG | SRCDEP_EAX | DSTDEP_EAX, INVALID, PAIR_NP | CYCLES(3),
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/* SUB SUB SUB SUB*/
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PAIR_UV | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_UV | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_UV | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_UV | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG,
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/* SUB SUB DAS*/
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PAIR_UV | CYCLES_REG | SRCDEP_EAX | SRCDEP_RM | DSTDEP_EAX, PAIR_UV | CYCLES_REG | SRCDEP_EAX | SRCDEP_RM | DSTDEP_EAX, INVALID, PAIR_NP | CYCLES(3),
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PAIR_UV | CYCLES_REG | SRCDEP_EAX | DSTDEP_EAX, PAIR_UV | CYCLES_REG | SRCDEP_EAX | DSTDEP_EAX, INVALID, PAIR_NP | CYCLES(3),
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/* XOR XOR XOR XOR*/
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/*30*/ PAIR_UV | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_UV | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_UV | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG, PAIR_UV | CYCLES_REG | SRCDEP_REG | SRCDEP_RM | DSTDEP_REG,
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/* XOR XOR AAA*/
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PAIR_UV | CYCLES_REG | SRCDEP_EAX | SRCDEP_RM | DSTDEP_EAX, PAIR_UV | CYCLES_REG | SRCDEP_EAX | SRCDEP_RM | DSTDEP_EAX, INVALID, PAIR_NP | CYCLES(3),
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PAIR_UV | CYCLES_REG | SRCDEP_EAX | DSTDEP_EAX, PAIR_UV | CYCLES_REG | SRCDEP_EAX | DSTDEP_EAX, INVALID, PAIR_NP | CYCLES(3),
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/* CMP CMP CMP CMP*/
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PAIR_UV | CYCLES_REG | SRCDEP_REG | SRCDEP_RM, PAIR_UV | CYCLES_REG | SRCDEP_REG | SRCDEP_RM, PAIR_UV | CYCLES_REG | SRCDEP_REG | SRCDEP_RM, PAIR_UV | CYCLES_REG | SRCDEP_RM | SRCDEP_REG,
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/* CMP CMP AAS*/
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PAIR_UV | CYCLES_REG | SRCDEP_EAX | SRCDEP_RM, PAIR_UV | CYCLES_REG | SRCDEP_EAX, INVALID, PAIR_NP | CYCLES(3),
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PAIR_UV | CYCLES_REG | SRCDEP_EAX, PAIR_UV | CYCLES_REG | SRCDEP_EAX, INVALID, PAIR_NP | CYCLES(3),
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/* INC EAX INC ECX INC EDX INC EBX*/
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/*40*/ PAIR_UV | CYCLES_REG | SRCDEP_EAX | DSTDEP_EAX, PAIR_UV | CYCLES_REG | SRCDEP_ECX | DSTDEP_ECX, PAIR_UV | CYCLES_REG | SRCDEP_EDX | DSTDEP_EDX, PAIR_UV | CYCLES_REG | SRCDEP_EBX | DSTDEP_EBX,
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@ -810,14 +817,20 @@ static uint32_t opcode_timings_df_mod3[8] =
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PAIR_NP | CYCLES(2), INVALID, INVALID, INVALID
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};
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static uint32_t opcode_timings_81[8] =
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{
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PAIR_UV | CYCLES_RMW | SRCDEP_REG | CYCLES_IMM1632, PAIR_UV | CYCLES_RMW | SRCDEP_REG | CYCLES_IMM1632, PAIR_UV | CYCLES_RMW | SRCDEP_REG | CYCLES_IMM1632, PAIR_UV | CYCLES_RMW | SRCDEP_REG | CYCLES_IMM1632,
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PAIR_UV | CYCLES_RMW | SRCDEP_REG | CYCLES_IMM1632, PAIR_UV | CYCLES_RMW | SRCDEP_REG | CYCLES_IMM1632, PAIR_UV | CYCLES_RMW | SRCDEP_REG | CYCLES_IMM1632, PAIR_UV | CYCLES_RM | SRCDEP_REG | CYCLES_IMM1632
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};
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static uint32_t opcode_timings_8x[8] =
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{
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PAIR_UV | CYCLES_RMW | SRCDEP_REG, PAIR_UV | CYCLES_RMW | SRCDEP_REG, PAIR_UV | CYCLES_RMW | SRCDEP_REG, PAIR_UV | CYCLES_RMW | SRCDEP_REG,
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PAIR_UV | CYCLES_RMW | SRCDEP_REG, PAIR_UV | CYCLES_RMW | SRCDEP_REG, PAIR_UV | CYCLES_RMW | SRCDEP_REG, PAIR_UV | CYCLES_RM | SRCDEP_REG
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PAIR_UV | CYCLES_RMW | SRCDEP_REG | CYCLES_IMM8, PAIR_UV | CYCLES_RMW | SRCDEP_REG | CYCLES_IMM8, PAIR_UV | CYCLES_RMW | SRCDEP_REG | CYCLES_IMM8, PAIR_UV | CYCLES_RMW | SRCDEP_REG | CYCLES_IMM8,
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PAIR_UV | CYCLES_RMW | SRCDEP_REG | CYCLES_IMM8, PAIR_UV | CYCLES_RMW | SRCDEP_REG | CYCLES_IMM8, PAIR_UV | CYCLES_RMW | SRCDEP_REG | CYCLES_IMM8, PAIR_UV | CYCLES_RM | SRCDEP_REG | CYCLES_IMM8
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};
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static int decode_delay;
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static uint8_t last_prefix;
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static int prefixes;
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static inline int COUNT(uint32_t c, int op_32)
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{
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@ -831,6 +844,10 @@ static inline int COUNT(uint32_t c, int op_32)
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return c & 0xffff;
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if ((c & PAIR_MASK) == PAIR_FX)
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return c & 0xffff;
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if ((c & PAIR_MASK) == PAIR_FXCH)
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return c & 0xffff;
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if ((c & PAIR_UV) && !(c & PAIR_FPU))
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c &= 3;
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switch (c & CYCLES_MASK)
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{
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case CYCLES_REG:
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@ -848,6 +865,80 @@ static inline int COUNT(uint32_t c, int op_32)
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return c;
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}
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static inline int codegen_timing_has_displacement(uint32_t fetchdat, int op_32)
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{
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if (op_32 & 0x200)
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{
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if ((fetchdat & 7) == 4 && (fetchdat & 0xc0) != 0xc0)
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{
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/*Has SIB*/
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if ((fetchdat & 0xc0) == 0x40 || (fetchdat & 0xc0) == 0x80 || (fetchdat & 0x700) == 0x500)
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return 1;
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}
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else
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{
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if ((fetchdat & 0xc0) == 0x40 || (fetchdat & 0xc0) == 0x80 || (fetchdat & 0xc7) == 0x05)
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return 1;
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}
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}
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else
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{
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if ((fetchdat & 0xc0) == 0x40 || (fetchdat & 0xc0) == 0x80 || (fetchdat & 0xc7) == 0x06)
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return 1;
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}
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return 0;
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}
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/*The instruction is only of interest here if it's longer than 7 bytes, as that's the
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limit on Pentium MMX parallel decoding*/
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static inline int codegen_timing_instr_length(uint32_t timing, uint32_t fetchdat, int op_32)
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{
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int len = prefixes;
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if ((timing & CYCLES_MASK) == CYCLES_RM || (timing & CYCLES_MASK) == CYCLES_RMW)
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{
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len += 2; /*Opcode + ModR/M*/
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if ((timing & CYCLES_HASIMM) == CYCLES_IMM8)
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len++;
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if ((timing & CYCLES_HASIMM) == CYCLES_IMM1632)
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len += (op_32 & 0x100) ? 4 : 2;
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if (op_32 & 0x200)
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{
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if ((fetchdat & 7) == 4 && (fetchdat & 0xc0) != 0xc0)
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{
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/* Has SIB*/
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len++;
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if ((fetchdat & 0xc0) == 0x40)
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len++;
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else if ((fetchdat & 0xc0) == 0x80)
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len += 4;
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else if ((fetchdat & 0x700) == 0x500)
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len += 4;
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}
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else
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{
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if ((fetchdat & 0xc0) == 0x40)
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len++;
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else if ((fetchdat & 0xc0) == 0x80)
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len += 4;
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else if ((fetchdat & 0xc7) == 0x05)
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len += 4;
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}
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}
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else
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{
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if ((fetchdat & 0xc0) == 0x40)
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len++;
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else if ((fetchdat & 0xc0) == 0x80)
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len += 2;
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else if ((fetchdat & 0xc7) == 0x06)
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len += 2;
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}
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}
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return len;
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}
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void codegen_timing_pentium_block_start()
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{
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u_pipe_full = decode_delay = 0;
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@ -857,10 +948,12 @@ void codegen_timing_pentium_start()
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{
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// decode_delay = 0;
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last_prefix = 0;
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prefixes = 0;
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}
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void codegen_timing_pentium_prefix(uint8_t prefix, uint32_t fetchdat)
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{
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prefixes++;
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if (cpu_hasMMX && prefix == 0x0f)
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{
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/*On Pentium MMX 0fh prefix is 'free'*/
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@ -943,12 +1036,18 @@ void codegen_timing_pentium_opcode(uint8_t opcode, uint32_t fetchdat, int op_32)
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default:
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switch (opcode)
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{
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case 0x80: case 0x81: case 0x82: case 0x83:
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case 0x80: case 0x82: case 0x83:
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timings = mod3 ? opcode_timings_mod3 : opcode_timings_8x;
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if (!mod3)
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opcode = (fetchdat >> 3) & 7;
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// pclog("timings 80 %p %p %p\n", (void *)timings, (void *)opcode_timings_mod3, (void *)opcode_timings_8x);
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break;
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case 0x81:
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timings = mod3 ? opcode_timings_mod3 : opcode_timings_81;
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if (!mod3)
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opcode = (fetchdat >> 3) & 7;
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// pclog("timings 80 %p %p %p\n", (void *)timings, (void *)opcode_timings_mod3, (void *)opcode_timings_8x);
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break;
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case 0xc0: case 0xc1: case 0xd0: case 0xd1: case 0xd2: case 0xd3:
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timings = mod3 ? opcode_timings_shift_mod3 : opcode_timings_shift;
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@ -996,24 +1095,39 @@ void codegen_timing_pentium_opcode(uint8_t opcode, uint32_t fetchdat, int op_32)
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if ((timings[opcode] & PAIR_V) && !(u_pipe_regmask & regmask) && !decode_delay)
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{
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int t1 = u_pipe_timings[u_pipe_opcode] & CYCLES_MASK;
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int t2 = timings[opcode] & CYCLES_MASK;
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int t_pair;
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int has_displacement;
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if (t1 < 0 || t2 < 0 || t1 > CYCLES_BRANCH || t2 > CYCLES_BRANCH)
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fatal("Pair out of range\n");
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if (timings[opcode] & CYCLES_HASIMM)
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has_displacement = codegen_timing_has_displacement(fetchdat, op_32);
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else
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has_displacement = 0;
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if (!has_displacement && (!cpu_hasMMX || codegen_timing_instr_length(timings[opcode], fetchdat, op_32) <= 7))
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{
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int t1 = u_pipe_timings[u_pipe_opcode] & CYCLES_MASK;
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int t2 = timings[opcode] & CYCLES_MASK;
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int t_pair;
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t_pair = pair_timings[t1][t2];
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if (t_pair < 1)
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fatal("Illegal pair timings : t1=%i t2=%i u_opcode=%02x v_opcode=%02x\n", t1, t2, u_pipe_opcode, opcode);
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if (!(u_pipe_timings[u_pipe_opcode] & PAIR_FPU))
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t1 &= 3;
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if (!(timings[opcode] & PAIR_FPU))
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t2 &= 3;
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if (t1 < 0 || t2 < 0 || t1 > CYCLES_BRANCH || t2 > CYCLES_BRANCH)
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fatal("Pair out of range\n");
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t_pair = pair_timings[t1][t2];
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if (t_pair < 1)
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fatal("Illegal pair timings : t1=%i t2=%i u_opcode=%02x v_opcode=%02x\n", t1, t2, u_pipe_opcode, opcode);
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// pclog("Paired timings : t_pair=%i t1=%i t2=%i u_opcode=%02x v_opcode=%02x %08x:%08x\n", t_pair, t1, t2, u_pipe_opcode, opcode, cs, pc);
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codegen_block_cycles += t_pair;
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decode_delay = (-t_pair) + 1;
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codegen_block_cycles += t_pair;
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decode_delay = (-t_pair) + 1;
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/*Instruction can pair with previous*/
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u_pipe_full = 0;
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return;
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/*Instruction can pair with previous*/
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u_pipe_full = 0;
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return;
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}
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}
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nopair:
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/*Instruction can not pair with previous*/
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@ -1026,13 +1140,23 @@ nopair:
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if ((timings[opcode] & PAIR_U) && !decode_delay)
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{
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/*Instruction might pair with next*/
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u_pipe_full = 1;
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u_pipe_opcode = opcode;
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u_pipe_timings = timings;
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u_pipe_op_32 = op_32;
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u_pipe_regmask = get_dstdep_mask(timings[opcode], fetchdat, bit8);
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return;
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int has_displacement;
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if (timings[opcode] & CYCLES_HASIMM)
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has_displacement = codegen_timing_has_displacement(fetchdat, op_32);
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else
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has_displacement = 0;
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if ((!has_displacement || cpu_hasMMX) && (!cpu_hasMMX || codegen_timing_instr_length(timings[opcode], fetchdat, op_32) <= 7))
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{
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/*Instruction might pair with next*/
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u_pipe_full = 1;
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u_pipe_opcode = opcode;
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u_pipe_timings = timings;
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u_pipe_op_32 = op_32;
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u_pipe_regmask = get_dstdep_mask(timings[opcode], fetchdat, bit8);
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return;
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}
|
||||
}
|
||||
/*Instruction can not pair and must run now*/
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue