Retro/pcem
Watch
1
0
Fork
You've already forked pcem
 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Added recompiled versions of ADC and SBC.

Browse source
This commit is contained in:
SarahW 2019-02-06 21:07:45 +00:00
commit d4d6a26283
5 changed files with 823 additions and 97 deletions
Download patch file Download diff file Expand all files Collapse all files

4
src/codegen_ops.c
View file

@ -27,7 +27,7 @@ RecompOpFn recomp_opcodes[512] =
/*16-bit data*/ /*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/ /* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropADD_b_rmw, ropADD_w_rmw, ropADD_b_rm, ropADD_w_rm, ropADD_AL_imm, ropADD_AX_imm, ropPUSH_ES_16, ropPOP_ES_16, ropOR_b_rmw, ropOR_w_rmw, ropOR_b_rm, ropOR_w_rm, ropOR_AL_imm, ropOR_AX_imm, ropPUSH_CS_16, NULL, /*00*/ ropADD_b_rmw, ropADD_w_rmw, ropADD_b_rm, ropADD_w_rm, ropADD_AL_imm, ropADD_AX_imm, ropPUSH_ES_16, ropPOP_ES_16, ropOR_b_rmw, ropOR_w_rmw, ropOR_b_rm, ropOR_w_rm, ropOR_AL_imm, ropOR_AX_imm, ropPUSH_CS_16, NULL,
/*10*/ NULL, NULL, NULL, NULL, NULL, NULL, ropPUSH_SS_16, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropPUSH_DS_16, ropPOP_DS_16, /*10*/ ropADC_b_rmw, ropADC_w_rmw, ropADC_b_rm, ropADC_w_rm, ropADC_AL_imm, ropADC_AX_imm, ropPUSH_SS_16, NULL, ropSBB_b_rmw, ropSBB_w_rmw, ropSBB_b_rm, ropSBB_w_rm, ropSBB_AL_imm, ropSBB_AX_imm, ropPUSH_DS_16, ropPOP_DS_16,
/*20*/ ropAND_b_rmw, ropAND_w_rmw, ropAND_b_rm, ropAND_w_rm, ropAND_AL_imm, ropAND_AX_imm, NULL, NULL, ropSUB_b_rmw, ropSUB_w_rmw, ropSUB_b_rm, ropSUB_w_rm, ropSUB_AL_imm, ropSUB_AX_imm, NULL, NULL, /*20*/ ropAND_b_rmw, ropAND_w_rmw, ropAND_b_rm, ropAND_w_rm, ropAND_AL_imm, ropAND_AX_imm, NULL, NULL, ropSUB_b_rmw, ropSUB_w_rmw, ropSUB_b_rm, ropSUB_w_rm, ropSUB_AL_imm, ropSUB_AX_imm, NULL, NULL,
/*30*/ ropXOR_b_rmw, ropXOR_w_rmw, ropXOR_b_rm, ropXOR_w_rm, ropXOR_AL_imm, ropXOR_AX_imm, NULL, NULL, ropCMP_b_rmw, ropCMP_w_rmw, ropCMP_b_rm, ropCMP_w_rm, ropCMP_AL_imm, ropCMP_AX_imm, NULL, NULL, /*30*/ ropXOR_b_rmw, ropXOR_w_rmw, ropXOR_b_rm, ropXOR_w_rm, ropXOR_AL_imm, ropXOR_AX_imm, NULL, NULL, ropCMP_b_rmw, ropCMP_w_rmw, ropCMP_b_rm, ropCMP_w_rm, ropCMP_AL_imm, ropCMP_AX_imm, NULL, NULL,
@ -49,7 +49,7 @@ RecompOpFn recomp_opcodes[512] =
/*32-bit data*/ /*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/ /* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropADD_b_rmw, ropADD_l_rmw, ropADD_b_rm, ropADD_l_rm, ropADD_AL_imm, ropADD_EAX_imm, ropPUSH_ES_32, ropPOP_ES_32, ropOR_b_rmw, ropOR_l_rmw, ropOR_b_rm, ropOR_l_rm, ropOR_AL_imm, ropOR_EAX_imm, ropPUSH_CS_32, NULL, /*00*/ ropADD_b_rmw, ropADD_l_rmw, ropADD_b_rm, ropADD_l_rm, ropADD_AL_imm, ropADD_EAX_imm, ropPUSH_ES_32, ropPOP_ES_32, ropOR_b_rmw, ropOR_l_rmw, ropOR_b_rm, ropOR_l_rm, ropOR_AL_imm, ropOR_EAX_imm, ropPUSH_CS_32, NULL,
/*10*/ NULL, NULL, NULL, NULL, NULL, NULL, ropPUSH_SS_32, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropPUSH_DS_32, ropPOP_DS_32, /*10*/ ropADC_b_rmw, ropADC_l_rmw, ropADC_b_rm, ropADC_l_rm, ropADC_AL_imm, ropADC_EAX_imm, ropPUSH_SS_32, NULL, ropSBB_b_rmw, ropSBB_l_rmw, ropSBB_b_rm, ropSBB_l_rm, ropSBB_AL_imm, ropSBB_EAX_imm, ropPUSH_DS_32, ropPOP_DS_32,
/*20*/ ropAND_b_rmw, ropAND_l_rmw, ropAND_b_rm, ropAND_l_rm, ropAND_AL_imm, ropAND_EAX_imm, NULL, NULL, ropSUB_b_rmw, ropSUB_l_rmw, ropSUB_b_rm, ropSUB_l_rm, ropSUB_AL_imm, ropSUB_EAX_imm, NULL, NULL, /*20*/ ropAND_b_rmw, ropAND_l_rmw, ropAND_b_rm, ropAND_l_rm, ropAND_AL_imm, ropAND_EAX_imm, NULL, NULL, ropSUB_b_rmw, ropSUB_l_rmw, ropSUB_b_rm, ropSUB_l_rm, ropSUB_AL_imm, ropSUB_EAX_imm, NULL, NULL,
/*30*/ ropXOR_b_rmw, ropXOR_l_rmw, ropXOR_b_rm, ropXOR_l_rm, ropXOR_AL_imm, ropXOR_EAX_imm, NULL, NULL, ropCMP_b_rmw, ropCMP_l_rmw, ropCMP_b_rm, ropCMP_l_rm, ropCMP_AL_imm, ropCMP_EAX_imm, NULL, NULL, /*30*/ ropXOR_b_rmw, ropXOR_l_rmw, ropXOR_b_rm, ropXOR_l_rm, ropXOR_AL_imm, ropXOR_EAX_imm, NULL, NULL, ropCMP_b_rmw, ropCMP_l_rmw, ropCMP_b_rm, ropCMP_l_rm, ropCMP_AL_imm, ropCMP_EAX_imm, NULL, NULL,

739
src/codegen_ops_arith.c
View file

@ -8,6 +8,263 @@
#include "codegen_ops.h" #include "codegen_ops.h"
#include "codegen_ops_arith.h" #include "codegen_ops_arith.h"
static inline void get_cf(ir_data_t *ir, int dest_reg)
{
uop_CALL_FUNC_RESULT(ir, dest_reg, CF_SET);
}
uint32_t ropADC_AL_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
uint8_t imm_data = fastreadb(cs + op_pc);
get_cf(ir, IREG_temp0);
uop_MOVZX(ir, IREG_flags_op1, IREG_AL);
uop_ADD_IMM(ir, IREG_AL, IREG_AL, imm_data);
uop_MOV_IMM(ir, IREG_flags_op2, imm_data);
uop_ADD(ir, IREG_AL, IREG_AL, IREG_temp0_B);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADC8);
uop_MOVZX(ir, IREG_flags_res, IREG_AL);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t ropADC_AX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
uint16_t imm_data = fastreadw(cs + op_pc);
get_cf(ir, IREG_temp0);
uop_MOVZX(ir, IREG_flags_op1, IREG_AX);
uop_ADD_IMM(ir, IREG_AX, IREG_AX, imm_data);
uop_MOV_IMM(ir, IREG_flags_op2, imm_data);
uop_ADD(ir, IREG_AX, IREG_AX, IREG_temp0_W);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADC16);
uop_MOVZX(ir, IREG_flags_res, IREG_AX);
codegen_flags_changed = 1;
return op_pc + 2;
}
uint32_t ropADC_EAX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
fetchdat = fastreadl(cs + op_pc);
get_cf(ir, IREG_temp0);
uop_MOV(ir, IREG_flags_op1, IREG_EAX);
uop_ADD_IMM(ir, IREG_EAX, IREG_EAX, fetchdat);
uop_MOV_IMM(ir, IREG_flags_op2, fetchdat);
uop_ADD(ir, IREG_EAX, IREG_EAX, IREG_temp0);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADC32);
uop_MOV(ir, IREG_flags_res, IREG_EAX);
codegen_flags_changed = 1;
return op_pc + 4;
}
uint32_t ropADC_b_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
//return 0;
get_cf(ir, IREG_temp1);
if ((fetchdat & 0xc0) == 0xc0)
{
int src_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_8(src_reg));
uop_ADD(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_8(src_reg));
}
else
{
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_temp0_B);
uop_ADD(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_temp0_B);
}
uop_ADD(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_temp1_B);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADC8);
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t ropADC_b_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg = (fetchdat >> 3) & 7;
get_cf(ir, IREG_temp1);
if ((fetchdat & 0xc0) == 0xc0)
{
int dest_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_8(src_reg));
uop_ADD(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_8(src_reg));
uop_ADD(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_temp1_B);
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
}
else
{
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
uop_ADD(ir, IREG_temp2_B, IREG_temp0_B, IREG_8(src_reg));
uop_ADD(ir, IREG_temp2_B, IREG_temp2_B, IREG_temp1_B);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp2_B);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_B);
uop_MOVZX(ir, IREG_flags_op2, IREG_8(src_reg));
uop_MOVZX(ir, IREG_flags_res, IREG_temp2_B);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADC8);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t ropADC_w_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
get_cf(ir, IREG_temp1);
if ((fetchdat & 0xc0) == 0xc0)
{
int src_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_16(src_reg));
uop_ADD(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_16(src_reg));
}
else
{
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_temp0_W);
uop_ADD(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp0_W);
}
uop_ADD(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp1_W);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADC16);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t ropADC_w_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg = (fetchdat >> 3) & 7;
get_cf(ir, IREG_temp1);
if ((fetchdat & 0xc0) == 0xc0)
{
int dest_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_16(src_reg));
uop_ADD(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_16(src_reg));
uop_ADD(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp1_W);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
}
else
{
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
uop_ADD(ir, IREG_temp2_W, IREG_temp0_W, IREG_16(src_reg));
uop_ADD(ir, IREG_temp2_W, IREG_temp2_W, IREG_temp1_W);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp2_W);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_W);
uop_MOVZX(ir, IREG_flags_op2, IREG_16(src_reg));
uop_MOVZX(ir, IREG_flags_res, IREG_temp2_W);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADC16);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t ropADC_l_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
get_cf(ir, IREG_temp1);
if ((fetchdat & 0xc0) == 0xc0)
{
int src_reg = fetchdat & 7;
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_MOV(ir, IREG_flags_op2, IREG_32(src_reg));
uop_ADD(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_32(src_reg));
}
else
{
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_flags_op2, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_ADD(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_flags_op2);
}
uop_ADD(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_temp1);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADC32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t ropADC_l_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg = (fetchdat >> 3) & 7;
get_cf(ir, IREG_temp1);
if ((fetchdat & 0xc0) == 0xc0)
{
int dest_reg = fetchdat & 7;
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_MOV(ir, IREG_flags_op2, IREG_32(src_reg));
uop_ADD(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_32(src_reg));
uop_ADD(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_temp1);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
}
else
{
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0, ireg_seg_base(target_seg), IREG_eaaddr);
uop_ADD(ir, IREG_temp2, IREG_temp0, IREG_32(src_reg));
uop_ADD(ir, IREG_temp2, IREG_temp2, IREG_temp1);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp2);
uop_MOV(ir, IREG_flags_op1, IREG_temp0);
uop_MOV(ir, IREG_flags_op2, IREG_32(src_reg));
uop_MOV(ir, IREG_flags_res, IREG_temp2);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADC32);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t ropADD_AL_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) uint32_t ropADD_AL_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{ {
uint8_t imm_data = fastreadb(cs + op_pc); uint8_t imm_data = fastreadb(cs + op_pc);
@ -462,6 +719,260 @@ uint32_t ropCMP_l_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_
return op_pc + 1; return op_pc + 1;
} }
uint32_t ropSBB_AL_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
uint8_t imm_data = fastreadb(cs + op_pc);
get_cf(ir, IREG_temp0);
uop_MOVZX(ir, IREG_flags_op1, IREG_AL);
uop_SUB_IMM(ir, IREG_AL, IREG_AL, imm_data);
uop_MOV_IMM(ir, IREG_flags_op2, imm_data);
uop_SUB(ir, IREG_AL, IREG_AL, IREG_temp0_B);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SBC8);
uop_MOVZX(ir, IREG_flags_res, IREG_AL);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t ropSBB_AX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
uint16_t imm_data = fastreadw(cs + op_pc);
get_cf(ir, IREG_temp0);
uop_MOVZX(ir, IREG_flags_op1, IREG_AX);
uop_SUB_IMM(ir, IREG_AX, IREG_AX, imm_data);
uop_MOV_IMM(ir, IREG_flags_op2, imm_data);
uop_SUB(ir, IREG_AX, IREG_AX, IREG_temp0_W);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SBC16);
uop_MOVZX(ir, IREG_flags_res, IREG_AX);
codegen_flags_changed = 1;
return op_pc + 2;
}
uint32_t ropSBB_EAX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
fetchdat = fastreadl(cs + op_pc);
get_cf(ir, IREG_temp0);
uop_MOV(ir, IREG_flags_op1, IREG_EAX);
uop_SUB_IMM(ir, IREG_EAX, IREG_EAX, fetchdat);
uop_MOV_IMM(ir, IREG_flags_op2, fetchdat);
uop_SUB(ir, IREG_EAX, IREG_EAX, IREG_temp0);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SBC32);
uop_MOV(ir, IREG_flags_res, IREG_EAX);
codegen_flags_changed = 1;
return op_pc + 4;
}
uint32_t ropSBB_b_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
get_cf(ir, IREG_temp1);
if ((fetchdat & 0xc0) == 0xc0)
{
int src_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_8(src_reg));
uop_SUB(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_8(src_reg));
}
else
{
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_temp0_B);
uop_SUB(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_temp0_B);
}
uop_SUB(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_temp1_B);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SBC8);
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t ropSBB_b_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg = (fetchdat >> 3) & 7;
get_cf(ir, IREG_temp1);
if ((fetchdat & 0xc0) == 0xc0)
{
int dest_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_8(src_reg));
uop_SUB(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_8(src_reg));
uop_SUB(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_temp1_B);
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
}
else
{
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
uop_SUB(ir, IREG_temp2_B, IREG_temp0_B, IREG_8(src_reg));
uop_SUB(ir, IREG_temp2_B, IREG_temp2_B, IREG_temp1_B);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp2_B);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_B);
uop_MOVZX(ir, IREG_flags_op2, IREG_8(src_reg));
uop_MOVZX(ir, IREG_flags_res, IREG_temp2_B);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SBC8);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t ropSBB_w_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
get_cf(ir, IREG_temp1);
if ((fetchdat & 0xc0) == 0xc0)
{
int src_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_16(src_reg));
uop_SUB(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_16(src_reg));
}
else
{
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_temp0_W);
uop_SUB(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp0_W);
}
uop_SUB(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp1_W);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SBC16);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t ropSBB_w_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg = (fetchdat >> 3) & 7;
get_cf(ir, IREG_temp1);
if ((fetchdat & 0xc0) == 0xc0)
{
int dest_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_16(src_reg));
uop_SUB(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_16(src_reg));
uop_SUB(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp1_W);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
}
else
{
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
uop_SUB(ir, IREG_temp2_W, IREG_temp0_W, IREG_16(src_reg));
uop_SUB(ir, IREG_temp2_W, IREG_temp2_W, IREG_temp1_W);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp2_W);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_W);
uop_MOVZX(ir, IREG_flags_op2, IREG_16(src_reg));
uop_MOVZX(ir, IREG_flags_res, IREG_temp2_W);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SBC16);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t ropSBB_l_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
get_cf(ir, IREG_temp1);
if ((fetchdat & 0xc0) == 0xc0)
{
int src_reg = fetchdat & 7;
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_MOV(ir, IREG_flags_op2, IREG_32(src_reg));
uop_SUB(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_32(src_reg));
}
else
{
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_flags_op2, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_SUB(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_flags_op2);
}
uop_SUB(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_temp1);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SBC32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t ropSBB_l_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg = (fetchdat >> 3) & 7;
get_cf(ir, IREG_temp1);
if ((fetchdat & 0xc0) == 0xc0)
{
int dest_reg = fetchdat & 7;
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_MOV(ir, IREG_flags_op2, IREG_32(src_reg));
uop_SUB(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_32(src_reg));
uop_SUB(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_temp1);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
}
else
{
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0, ireg_seg_base(target_seg), IREG_eaaddr);
uop_SUB(ir, IREG_temp2, IREG_temp0, IREG_32(src_reg));
uop_SUB(ir, IREG_temp2, IREG_temp2, IREG_temp1);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp2);
uop_MOV(ir, IREG_flags_op1, IREG_temp0);
uop_MOV(ir, IREG_flags_op2, IREG_32(src_reg));
uop_MOV(ir, IREG_flags_res, IREG_temp2);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SBC32);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t ropSUB_AL_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) uint32_t ropSUB_AL_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{ {
uint8_t imm_data = fastreadb(cs + op_pc); uint8_t imm_data = fastreadb(cs + op_pc);
@ -697,9 +1208,6 @@ uint32_t ropSUB_l_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_
uint32_t rop80(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) uint32_t rop80(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{ {
if ((fetchdat & 0x30) == 0x10) /*ADC/SBB*/
return 0;
if ((fetchdat & 0xc0) == 0xc0) if ((fetchdat & 0xc0) == 0xc0)
{ {
int dest_reg = fetchdat & 7; int dest_reg = fetchdat & 7;
@ -721,6 +1229,26 @@ uint32_t rop80(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetch
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg)); uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
break; break;
case 0x10: /*ADC*/
get_cf(ir, IREG_temp1);
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
uop_ADD_IMM(ir, IREG_8(dest_reg), IREG_8(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_ADD(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_temp1_B);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADC8);
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
break;
case 0x18: /*SBB*/
get_cf(ir, IREG_temp1);
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
uop_SUB_IMM(ir, IREG_8(dest_reg), IREG_8(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_SUB(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_temp1_B);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SBC8);
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
break;
case 0x20: /*AND*/ case 0x20: /*AND*/
uop_AND_IMM(ir, IREG_8(dest_reg), IREG_8(dest_reg), imm); uop_AND_IMM(ir, IREG_8(dest_reg), IREG_8(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN8); uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN8);
@ -785,6 +1313,28 @@ uint32_t rop80(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetch
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN8); uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN8);
break; break;
case 0x10: /*ADC*/
get_cf(ir, IREG_temp2);
uop_ADD_IMM(ir, IREG_temp1_B, IREG_temp0_B, imm);
uop_ADD(ir, IREG_temp1_B, IREG_temp1_B, IREG_temp2_B);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_B);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_B);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADC8);
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_B);
break;
case 0x18: /*SBB*/
get_cf(ir, IREG_temp2);
uop_SUB_IMM(ir, IREG_temp1_B, IREG_temp0_B, imm);
uop_SUB(ir, IREG_temp1_B, IREG_temp1_B, IREG_temp2_B);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_B);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_B);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SBC8);
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_B);
break;
case 0x20: /*AND*/ case 0x20: /*AND*/
uop_AND_IMM(ir, IREG_temp0_B, IREG_temp0_B, imm); uop_AND_IMM(ir, IREG_temp0_B, IREG_temp0_B, imm);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_B); uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_B);
@ -826,9 +1376,6 @@ uint32_t rop80(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetch
} }
uint32_t rop81_w(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) uint32_t rop81_w(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{ {
if ((fetchdat & 0x30) == 0x10) /*ADC/SBB*/
return 0;
if ((fetchdat & 0xc0) == 0xc0) if ((fetchdat & 0xc0) == 0xc0)
{ {
int dest_reg = fetchdat & 7; int dest_reg = fetchdat & 7;
@ -850,6 +1397,26 @@ uint32_t rop81_w(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fet
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg)); uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
break; break;
case 0x10: /*ADC*/
get_cf(ir, IREG_temp1);
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
uop_ADD_IMM(ir, IREG_16(dest_reg), IREG_16(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_ADD(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp1_W);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADC16);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
break;
case 0x18: /*SBB*/
get_cf(ir, IREG_temp1);
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
uop_SUB_IMM(ir, IREG_16(dest_reg), IREG_16(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_SUB(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp1_W);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SBC16);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
break;
case 0x20: /*AND*/ case 0x20: /*AND*/
uop_AND_IMM(ir, IREG_16(dest_reg), IREG_16(dest_reg), imm); uop_AND_IMM(ir, IREG_16(dest_reg), IREG_16(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN16); uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN16);
@ -914,6 +1481,28 @@ uint32_t rop81_w(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fet
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN16); uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN16);
break; break;
case 0x10: /*ADC*/
get_cf(ir, IREG_temp2);
uop_ADD_IMM(ir, IREG_temp1_W, IREG_temp0_W, imm);
uop_ADD(ir, IREG_temp1_W, IREG_temp1_W, IREG_temp2_W);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_W);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_W);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADC16);
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_W);
break;
case 0x18: /*SBB*/
get_cf(ir, IREG_temp2);
uop_SUB_IMM(ir, IREG_temp1_W, IREG_temp0_W, imm);
uop_SUB(ir, IREG_temp1_W, IREG_temp1_W, IREG_temp2_W);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_W);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_W);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SBC16);
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_W);
break;
case 0x20: /*AND*/ case 0x20: /*AND*/
uop_AND_IMM(ir, IREG_temp0_W, IREG_temp0_W, imm); uop_AND_IMM(ir, IREG_temp0_W, IREG_temp0_W, imm);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_W); uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_W);
@ -955,9 +1544,6 @@ uint32_t rop81_w(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fet
} }
uint32_t rop81_l(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) uint32_t rop81_l(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{ {
if ((fetchdat & 0x30) == 0x10) /*ADC/SBB*/
return 0;
if ((fetchdat & 0xc0) == 0xc0) if ((fetchdat & 0xc0) == 0xc0)
{ {
int dest_reg = fetchdat & 7; int dest_reg = fetchdat & 7;
@ -979,6 +1565,26 @@ uint32_t rop81_l(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fet
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg)); uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
break; break;
case 0x10: /*ADC*/
get_cf(ir, IREG_temp1);
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_ADD_IMM(ir, IREG_32(dest_reg), IREG_32(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_ADD(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_temp1);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADC32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
break;
case 0x18: /*SBB*/
get_cf(ir, IREG_temp1);
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_SUB_IMM(ir, IREG_32(dest_reg), IREG_32(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_SUB(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_temp1);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SBC32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
break;
case 0x20: /*AND*/ case 0x20: /*AND*/
uop_AND_IMM(ir, IREG_32(dest_reg), IREG_32(dest_reg), imm); uop_AND_IMM(ir, IREG_32(dest_reg), IREG_32(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN32); uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN32);
@ -1042,6 +1648,28 @@ uint32_t rop81_l(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fet
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN32); uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN32);
break; break;
case 0x10: /*ADC*/
get_cf(ir, IREG_temp2);
uop_ADD_IMM(ir, IREG_temp1, IREG_temp0, imm);
uop_ADD(ir, IREG_temp1, IREG_temp1, IREG_temp2);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1);
uop_MOV(ir, IREG_flags_op1, IREG_temp0);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADC32);
uop_MOV(ir, IREG_flags_res, IREG_temp1);
break;
case 0x18: /*SBB*/
get_cf(ir, IREG_temp2);
uop_SUB_IMM(ir, IREG_temp1, IREG_temp0, imm);
uop_SUB(ir, IREG_temp1, IREG_temp1, IREG_temp2);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1);
uop_MOV(ir, IREG_flags_op1, IREG_temp0);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SBC32);
uop_MOV(ir, IREG_flags_res, IREG_temp1);
break;
case 0x20: /*AND*/ case 0x20: /*AND*/
uop_AND_IMM(ir, IREG_temp0, IREG_temp0, imm); uop_AND_IMM(ir, IREG_temp0, IREG_temp0, imm);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0); uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0);
@ -1083,9 +1711,6 @@ uint32_t rop81_l(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fet
uint32_t rop83_w(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) uint32_t rop83_w(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{ {
if ((fetchdat & 0x30) == 0x10) /*ADC/SBB*/
return 0;
if ((fetchdat & 0xc0) == 0xc0) if ((fetchdat & 0xc0) == 0xc0)
{ {
int dest_reg = fetchdat & 7; int dest_reg = fetchdat & 7;
@ -1107,6 +1732,26 @@ uint32_t rop83_w(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fet
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg)); uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
break; break;
case 0x10: /*ADC*/
get_cf(ir, IREG_temp1);
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
uop_ADD_IMM(ir, IREG_16(dest_reg), IREG_16(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_ADD(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp1_W);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADC16);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
break;
case 0x18: /*SBB*/
get_cf(ir, IREG_temp1);
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
uop_SUB_IMM(ir, IREG_16(dest_reg), IREG_16(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_SUB(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp1_W);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SBC16);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
break;
case 0x20: /*AND*/ case 0x20: /*AND*/
uop_AND_IMM(ir, IREG_16(dest_reg), IREG_16(dest_reg), imm); uop_AND_IMM(ir, IREG_16(dest_reg), IREG_16(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN16); uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN16);
@ -1171,6 +1816,28 @@ uint32_t rop83_w(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fet
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN16); uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN16);
break; break;
case 0x10: /*ADC*/
get_cf(ir, IREG_temp2);
uop_ADD_IMM(ir, IREG_temp1_W, IREG_temp0_W, imm);
uop_ADD(ir, IREG_temp1_W, IREG_temp1_W, IREG_temp2_W);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_W);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_W);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADC16);
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_W);
break;
case 0x18: /*SBB*/
get_cf(ir, IREG_temp2);
uop_SUB_IMM(ir, IREG_temp1_W, IREG_temp0_W, imm);
uop_SUB(ir, IREG_temp1_W, IREG_temp1_W, IREG_temp2_W);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_W);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_W);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SBC16);
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_W);
break;
case 0x20: /*AND*/ case 0x20: /*AND*/
uop_AND_IMM(ir, IREG_temp0_W, IREG_temp0_W, imm); uop_AND_IMM(ir, IREG_temp0_W, IREG_temp0_W, imm);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_W); uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_W);
@ -1212,11 +1879,6 @@ uint32_t rop83_w(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fet
} }
uint32_t rop83_l(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) uint32_t rop83_l(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{ {
uint32_t imm;
if ((fetchdat & 0x30) == 0x10) /*ADC/SBB*/
return 0;
if ((fetchdat & 0xc0) == 0xc0) if ((fetchdat & 0xc0) == 0xc0)
{ {
int dest_reg = fetchdat & 7; int dest_reg = fetchdat & 7;
@ -1238,6 +1900,26 @@ uint32_t rop83_l(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fet
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg)); uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
break; break;
case 0x10: /*ADC*/
get_cf(ir, IREG_temp1);
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_ADD_IMM(ir, IREG_32(dest_reg), IREG_32(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_ADD(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_temp1);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADC32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
break;
case 0x18: /*SBB*/
get_cf(ir, IREG_temp1);
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_SUB_IMM(ir, IREG_32(dest_reg), IREG_32(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_SUB(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_temp1);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SBC32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
break;
case 0x20: /*AND*/ case 0x20: /*AND*/
uop_AND_IMM(ir, IREG_32(dest_reg), IREG_32(dest_reg), imm); uop_AND_IMM(ir, IREG_32(dest_reg), IREG_32(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN32); uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN32);
@ -1272,6 +1954,7 @@ uint32_t rop83_l(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fet
else else
{ {
x86seg *target_seg; x86seg *target_seg;
uint32_t imm;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
@ -1300,6 +1983,28 @@ uint32_t rop83_l(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fet
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN32); uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN32);
break; break;
case 0x10: /*ADC*/
get_cf(ir, IREG_temp2);
uop_ADD_IMM(ir, IREG_temp1, IREG_temp0, imm);
uop_ADD(ir, IREG_temp1, IREG_temp1, IREG_temp2);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1);
uop_MOV(ir, IREG_flags_op1, IREG_temp0);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADC32);
uop_MOV(ir, IREG_flags_res, IREG_temp1);
break;
case 0x18: /*SBB*/
get_cf(ir, IREG_temp2);
uop_SUB_IMM(ir, IREG_temp1, IREG_temp0, imm);
uop_SUB(ir, IREG_temp1, IREG_temp1, IREG_temp2);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1);
uop_MOV(ir, IREG_flags_op1, IREG_temp0);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SBC32);
uop_MOV(ir, IREG_flags_res, IREG_temp1);
break;
case 0x20: /*AND*/ case 0x20: /*AND*/
uop_AND_IMM(ir, IREG_temp0, IREG_temp0, imm); uop_AND_IMM(ir, IREG_temp0, IREG_temp0, imm);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0); uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0);

20
src/codegen_ops_arith.h
View file

@ -1,3 +1,13 @@
uint32_t ropADC_AL_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropADC_AX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropADC_EAX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropADC_b_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropADC_b_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropADC_w_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropADC_w_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropADC_l_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropADC_l_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropADD_AL_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc); uint32_t ropADD_AL_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropADD_AX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc); uint32_t ropADD_AX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropADD_EAX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc); uint32_t ropADD_EAX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
@ -18,6 +28,16 @@ uint32_t ropCMP_w_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_
uint32_t ropCMP_l_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc); uint32_t ropCMP_l_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropCMP_l_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc); uint32_t ropCMP_l_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropSBB_AL_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropSBB_AX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropSBB_EAX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropSBB_b_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropSBB_b_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropSBB_w_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropSBB_w_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropSBB_l_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropSBB_l_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropSUB_AL_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc); uint32_t ropSUB_AL_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropSUB_AX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc); uint32_t ropSUB_AX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropSUB_EAX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc); uint32_t ropSUB_EAX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);

1
src/codegen_reg.h
View file

@ -170,6 +170,7 @@ enum
IREG_temp0_B = IREG_temp0 + IREG_SIZE_B, IREG_temp0_B = IREG_temp0 + IREG_SIZE_B,
IREG_temp1_B = IREG_temp1 + IREG_SIZE_B, IREG_temp1_B = IREG_temp1 + IREG_SIZE_B,
IREG_temp2_B = IREG_temp2 + IREG_SIZE_B,
IREG_temp0_D = IREG_temp0d + IREG_SIZE_D, IREG_temp0_D = IREG_temp0d + IREG_SIZE_D,
IREG_temp1_D = IREG_temp1d + IREG_SIZE_D, IREG_temp1_D = IREG_temp1d + IREG_SIZE_D,

10
src/x86_flags.h
View file

@ -292,9 +292,9 @@ static inline int CF_SET()
switch (cpu_state.flags_op) switch (cpu_state.flags_op)
{ {
case FLAGS_ADD8: case FLAGS_ADD8:
return (cpu_state.flags_op1 + cpu_state.flags_op2) & 0x100; return ((cpu_state.flags_op1 + cpu_state.flags_op2) & 0x100) ? 1 : 0;
case FLAGS_ADD16: case FLAGS_ADD16:
return (cpu_state.flags_op1 + cpu_state.flags_op2) & 0x10000; return ((cpu_state.flags_op1 + cpu_state.flags_op2) & 0x10000) ? 1 : 0;
case FLAGS_ADD32: case FLAGS_ADD32:
return (cpu_state.flags_res < cpu_state.flags_op1); return (cpu_state.flags_res < cpu_state.flags_op1);
@ -320,11 +320,11 @@ static inline int CF_SET()
(cpu_state.flags_op1 == cpu_state.flags_op2 && cpu_state.flags_res != 0); (cpu_state.flags_op1 == cpu_state.flags_op2 && cpu_state.flags_res != 0);
case FLAGS_SHL8: case FLAGS_SHL8:
return (cpu_state.flags_op1 << (cpu_state.flags_op2 - 1)) & 0x80; return ((cpu_state.flags_op1 << (cpu_state.flags_op2 - 1)) & 0x80) ? 1 : 0;
case FLAGS_SHL16: case FLAGS_SHL16:
return (cpu_state.flags_op1 << (cpu_state.flags_op2 - 1)) & 0x8000; return ((cpu_state.flags_op1 << (cpu_state.flags_op2 - 1)) & 0x8000) ? 1 : 0;
case FLAGS_SHL32: case FLAGS_SHL32:
return (cpu_state.flags_op1 << (cpu_state.flags_op2 - 1)) & 0x80000000; return ((cpu_state.flags_op1 << (cpu_state.flags_op2 - 1)) & 0x80000000) ? 1 : 0;
case FLAGS_SHR8: case FLAGS_SHR8:
case FLAGS_SHR16: case FLAGS_SHR16: