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PIIX command register now honours bit 2.

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All IDE interrupts now set PIIX IDE Interrupt Status.
Helps BeOS.
This commit is contained in:
TomW 2015-05-03 16:10:11 +01:00
commit d2206f91c9
2 changed files with 5 additions and 5 deletions
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3
src/ide.c
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@ -175,6 +175,7 @@ static inline void ide_irq_raise(IDE *ide)
#else #else
// if (ide->board && !ide->irqstat) pclog("IDE_IRQ_RAISE\n"); // if (ide->board && !ide->irqstat) pclog("IDE_IRQ_RAISE\n");
picint((ide->board)?(1<<15):(1<<14)); picint((ide->board)?(1<<15):(1<<14));
ide_bus_master_set_irq(ide->board);
#endif #endif
} }
ide->irqstat=1; ide->irqstat=1;
@ -1197,7 +1198,6 @@ void callbackide(int ide_board)
else else
{ {
ide_irq_raise(ide); ide_irq_raise(ide);
ide_bus_master_set_irq(ide_board);
} }
} }
} }
@ -1281,7 +1281,6 @@ void callbackide(int ide_board)
else else
{ {
ide_irq_raise(ide); ide_irq_raise(ide);
ide_bus_master_set_irq(ide_board);
} }
} }
} }

7
src/piix.c
View file

@ -29,7 +29,7 @@ void piix_write(int func, int addr, uint8_t val, void *priv)
switch (addr) switch (addr)
{ {
case 0x04: case 0x04:
card_piix_ide[0x04] = (card_piix_ide[0x04] & ~1) | (val & 1); card_piix_ide[0x04] = (card_piix_ide[0x04] & ~5) | (val & 5);
break; break;
case 0x07: case 0x07:
card_piix_ide[0x07] = (card_piix_ide[0x07] & ~0x38) | (val & 0x38); card_piix_ide[0x07] = (card_piix_ide[0x07] & ~0x38) | (val & 0x38);
@ -70,11 +70,12 @@ void piix_write(int func, int addr, uint8_t val, void *priv)
card_piix_ide[0x43] = val; card_piix_ide[0x43] = val;
break; break;
} }
if ((addr & ~3) == 0x20) /*Bus master base address*/ if (addr == 4 || (addr & ~3) == 0x20) /*Bus master base address*/
{ {
uint16_t base = (card_piix_ide[0x20] & 0xf0) | (card_piix_ide[0x21] << 8); uint16_t base = (card_piix_ide[0x20] & 0xf0) | (card_piix_ide[0x21] << 8);
io_removehandler(0, 0x10000, piix_bus_master_read, NULL, NULL, piix_bus_master_write, NULL, NULL, NULL); io_removehandler(0, 0x10000, piix_bus_master_read, NULL, NULL, piix_bus_master_write, NULL, NULL, NULL);
io_sethandler(base, 0x10, piix_bus_master_read, NULL, NULL, piix_bus_master_write, NULL, NULL, NULL); if (card_piix_ide[0x04] & 1)
io_sethandler(base, 0x10, piix_bus_master_read, NULL, NULL, piix_bus_master_write, NULL, NULL, NULL);
} }
// pclog("PIIX write %02X %02X\n", addr, val); // pclog("PIIX write %02X %02X\n", addr, val);
} }