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Replace cpu_has* flags with single cpu_features variable and cpu_has_feature() getter.

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This commit is contained in:
SarahW 2019-02-08 21:22:53 +00:00
commit ce4436054d
8 changed files with 53 additions and 87 deletions
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10
src/codegen_timing_pentium.c
View file

@ -815,7 +815,7 @@ static inline int COUNT(uint64_t timings, uint64_t deps, int op_32)
case CYCLES_RMW:
return 3;
case CYCLES_BRANCH:
return cpu_hasMMX ? 1 : 2;
return cpu_has_feature(CPU_FEATURE_MMX) ? 1 : 2;
}
fatal("Illegal COUNT %016llx\n", timings);
@ -949,13 +949,13 @@ void codegen_timing_pentium_prefix(uint8_t prefix, uint32_t fetchdat)
last_prefix = prefix;
return;
}
if (cpu_hasMMX && prefix == 0x0f)
if (cpu_has_feature(CPU_FEATURE_MMX) && prefix == 0x0f)
{
/*On Pentium MMX 0fh prefix is 'free'*/
last_prefix = prefix;
return;
}
if (cpu_hasMMX && (prefix == 0x66 || prefix == 0x67))
if (cpu_has_feature(CPU_FEATURE_MMX) && (prefix == 0x66 || prefix == 0x67))
{
/*On Pentium MMX 66h and 67h prefixes take 2 clocks*/
decode_delay_offset += 2;
@ -1239,7 +1239,7 @@ void codegen_timing_pentium_opcode(uint8_t opcode, uint32_t fetchdat, int op_32,
else
has_displacement = 0;
if (!has_displacement && (!cpu_hasMMX || codegen_timing_instr_length(timings[opcode], fetchdat, op_32) <= 7))
if (!has_displacement && (!cpu_has_feature(CPU_FEATURE_MMX) || codegen_timing_instr_length(timings[opcode], fetchdat, op_32) <= 7))
{
int t1 = u_pipe_timings[u_pipe_opcode] & CYCLES_MASK;
int t2 = timings[opcode] & CYCLES_MASK;
@ -1292,7 +1292,7 @@ nopair:
else
has_displacement = 0;
if ((!has_displacement || cpu_hasMMX) && (!cpu_hasMMX || codegen_timing_instr_length(timings[opcode], fetchdat, op_32) <= 7))
if ((!has_displacement || cpu_has_feature(CPU_FEATURE_MMX)) && (!cpu_has_feature(CPU_FEATURE_MMX) || codegen_timing_instr_length(timings[opcode], fetchdat, op_32) <= 7))
{
/*Instruction might pair with next*/
u_pipe_full = 1;

90
src/cpu.c
View file

@ -7,6 +7,8 @@
#include "pci.h"
#include "codegen.h"
uint32_t cpu_features;
static int cpu_turbo_speed, cpu_nonturbo_speed;
static int cpu_turbo = 1;
@ -82,12 +84,6 @@ int cpu_multi;
int cpu_iscyrix;
int cpu_16bitbus;
int cpu_busspeed;
int cpu_hasrdtsc;
int cpu_hasMMX, cpu_hasMSR;
int cpu_hasCR4;
int cpu_hasCX8;
int cpu_hasVME;
int cpu_has3DNOW;
int cpu_use_dynarec;
int cpu_cyrix_alignment;
@ -580,12 +576,6 @@ void cpu_set()
if (cpu_s->multi)
cpu_busspeed = cpu_s->rspeed / cpu_s->multi;
cpu_multi = cpu_s->multi;
cpu_hasrdtsc = 0;
cpu_hasMMX = 0;
cpu_hasMSR = 0;
cpu_hasCR4 = 0;
cpu_hasCX8 = 0;
cpu_has3DNOW = 0;
ccr0 = ccr1 = ccr2 = ccr3 = ccr4 = ccr5 = ccr6 = 0;
has_vlb = (cpu_s->cpu_type >= CPU_i486SX) && (cpu_s->cpu_type <= CPU_Cx5x86);
@ -885,8 +875,7 @@ void cpu_set()
break;
case CPU_iDX4:
cpu_hasCR4 = 1;
cpu_hasVME = 1;
cpu_features = CPU_FEATURE_CR4 | CPU_FEATURE_VME;
cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_VME;
case CPU_i486SX:
case CPU_i486DX:
@ -1032,10 +1021,8 @@ void cpu_set()
timing_mml = 3;
timing_bt = 3-1; /*branch taken*/
timing_bnt = 1; /*branch not taken*/
cpu_hasrdtsc = 1;
cpu_features = CPU_FEATURE_RDTSC | CPU_FEATURE_MMX | CPU_FEATURE_MSR | CPU_FEATURE_CR4;
msr.fcr = (1 << 8) | (1 << 16);
cpu_hasMMX = cpu_hasMSR = 1;
cpu_hasCR4 = 1;
cpu_CR4_mask = CR4_TSD | CR4_DE | CR4_MCE | CR4_PCE;
/*unknown*/
timing_int_rm = 26;
@ -1072,10 +1059,8 @@ void cpu_set()
timing_mml = 3;
timing_bt = 3-1; /*branch taken*/
timing_bnt = 1; /*branch not taken*/
cpu_hasrdtsc = 1;
cpu_features = CPU_FEATURE_RDTSC | CPU_FEATURE_MMX | CPU_FEATURE_MSR | CPU_FEATURE_CR4 | CPU_FEATURE_3DNOW;
msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) | (1 << 16) | (1 << 18) | (1 << 19) | (1 << 20) | (1 << 21);
cpu_hasMMX = cpu_hasMSR = cpu_has3DNOW = 1;
cpu_hasCR4 = 1;
cpu_CR4_mask = CR4_TSD | CR4_DE | CR4_MCE | CR4_PCE;
/*unknown*/
timing_int_rm = 26;
@ -1132,12 +1117,8 @@ void cpu_set()
timing_jmp_pm = 3;
timing_jmp_pm_gate = 18;
timing_misaligned = 3;
cpu_hasrdtsc = 1;
cpu_features = CPU_FEATURE_RDTSC | CPU_FEATURE_MSR | CPU_FEATURE_CR4 | CPU_FEATURE_VME;
msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) | (1 << 16) | (1 << 19) | (1 << 21);
cpu_hasMMX = 0;
cpu_hasMSR = 1;
cpu_hasCR4 = 1;
cpu_hasVME = 1;
cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE | CR4_PCE;
codegen_timing_set(&codegen_timing_pentium);
break;
@ -1173,12 +1154,8 @@ void cpu_set()
timing_jmp_pm = 3;
timing_jmp_pm_gate = 18;
timing_misaligned = 3;
cpu_hasrdtsc = 1;
cpu_features = CPU_FEATURE_RDTSC | CPU_FEATURE_MSR | CPU_FEATURE_CR4 | CPU_FEATURE_VME | CPU_FEATURE_MMX;
msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) | (1 << 16) | (1 << 19) | (1 << 21);
cpu_hasMMX = 1;
cpu_hasMSR = 1;
cpu_hasCR4 = 1;
cpu_hasVME = 1;
cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE | CR4_PCE;
codegen_timing_set(&codegen_timing_pentium);
break;
@ -1214,11 +1191,8 @@ void cpu_set()
timing_jmp_pm_gate = 14;
timing_misaligned = 2;
cpu_cyrix_alignment = 1;
cpu_hasrdtsc = 1;
cpu_features = CPU_FEATURE_RDTSC;
msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) | (1 << 16) | (1 << 19) | (1 << 21);
cpu_hasMMX = 0;
cpu_hasMSR = 0;
cpu_hasCR4 = 0;
codegen_timing_set(&codegen_timing_686);
CPUID = 0; /*Disabled on powerup by default*/
break;
@ -1254,11 +1228,8 @@ void cpu_set()
timing_jmp_pm_gate = 14;
timing_misaligned = 2;
cpu_cyrix_alignment = 1;
cpu_hasrdtsc = 1;
cpu_features = CPU_FEATURE_RDTSC;
msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) | (1 << 16) | (1 << 19) | (1 << 21);
cpu_hasMMX = 0;
cpu_hasMSR = 0;
cpu_hasCR4 = 0;
codegen_timing_set(&codegen_timing_686);
ccr4 = 0x80;
break;
@ -1275,11 +1246,8 @@ void cpu_set()
timing_mml = 2;
timing_bt = 5-1; /*branch taken*/
timing_bnt = 1; /*branch not taken*/
cpu_hasrdtsc = 1;
cpu_features = CPU_FEATURE_RDTSC | CPU_FEATURE_MSR | CPU_FEATURE_CR4;
msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) | (1 << 16) | (1 << 19) | (1 << 21);
cpu_hasMMX = 0;
cpu_hasMSR = 1;
cpu_hasCR4 = 1;
cpu_CR4_mask = CR4_TSD | CR4_DE | CR4_PCE;
codegen_timing_set(&codegen_timing_686);
break;
@ -1328,11 +1296,8 @@ void cpu_set()
timing_jmp_pm_gate = 14;
timing_misaligned = 2;
cpu_cyrix_alignment = 1;
cpu_hasrdtsc = 1;
cpu_features = CPU_FEATURE_RDTSC | CPU_FEATURE_MSR | CPU_FEATURE_CR4 | CPU_FEATURE_MMX;
msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) | (1 << 16) | (1 << 19) | (1 << 21);
cpu_hasMMX = 1;
cpu_hasMSR = 1;
cpu_hasCR4 = 1;
cpu_CR4_mask = CR4_TSD | CR4_DE | CR4_PCE;
codegen_timing_set(&codegen_timing_686);
ccr4 = 0x80;
@ -1369,12 +1334,8 @@ void cpu_set()
timing_jmp_pm = 3;
timing_jmp_pm_gate = 18;
timing_misaligned = 3;
cpu_hasrdtsc = 1;
cpu_features = CPU_FEATURE_RDTSC | CPU_FEATURE_MSR | CPU_FEATURE_CR4 | CPU_FEATURE_VME | CPU_FEATURE_MMX;
msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) | (1 << 16) | (1 << 19) | (1 << 21);
cpu_hasMMX = 1;
cpu_hasMSR = 1;
cpu_hasCR4 = 1;
cpu_hasVME = 1;
cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE;
codegen_timing_set(&codegen_timing_k6);
break;
@ -1413,12 +1374,8 @@ void cpu_set()
timing_jmp_pm = 3;
timing_jmp_pm_gate = 18;
timing_misaligned = 3;
cpu_hasrdtsc = 1;
cpu_features = CPU_FEATURE_RDTSC | CPU_FEATURE_MSR | CPU_FEATURE_CR4 | CPU_FEATURE_VME | CPU_FEATURE_MMX | CPU_FEATURE_3DNOW;
msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) | (1 << 16) | (1 << 19) | (1 << 21);
cpu_hasMMX = 1;
cpu_hasMSR = 1;
cpu_hasCR4 = 1;
cpu_hasVME = 1;
cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE;
codegen_timing_set(&codegen_timing_k6);
break;
@ -1525,7 +1482,7 @@ void cpu_CPUID()
EAX = 0x540;
EBX = ECX = 0;
EDX = CPUID_FPU | CPUID_TSC | CPUID_MSR;
if (cpu_hasCX8)
if (cpu_has_feature(CPU_FEATURE_CX8))
EDX |= CPUID_CMPXCHG8B;
if (msr.fcr & (1 << 9))
EDX |= CPUID_MMX;
@ -1556,7 +1513,7 @@ void cpu_CPUID()
EAX = 0x580;
EBX = ECX = 0;
EDX = CPUID_FPU | CPUID_TSC | CPUID_MSR;
if (cpu_hasCX8)
if (cpu_has_feature(CPU_FEATURE_CX8))
EDX |= CPUID_CMPXCHG8B;
if (msr.fcr & (1 << 9))
EDX |= CPUID_MMX;
@ -1567,11 +1524,11 @@ void cpu_CPUID()
case 0x80000001:
EAX = 0x580;
EDX = CPUID_FPU | CPUID_TSC | CPUID_MSR;
if (cpu_hasCX8)
if (cpu_has_feature(CPU_FEATURE_CX8))
EDX |= CPUID_CMPXCHG8B;
if (msr.fcr & (1 << 9))
EDX |= CPUID_MMX;
if (cpu_has3DNOW)
if (cpu_has_feature(CPU_FEATURE_3DNOW))
EDX |= CPUID_3DNOW;
break;
@ -2021,15 +1978,18 @@ void cpu_WRMSR()
break;
case 0x107:
msr.fcr = EAX;
cpu_hasMMX = EAX & (1 << 9);
if (EAX & (1 << 9))
cpu_features |= CPU_FEATURE_MMX;
else
cpu_features &= ~CPU_FEATURE_MMX;
if (EAX & (1 << 1))
cpu_hasCX8 = 1;
cpu_features |= CPU_FEATURE_CX8;
else
cpu_hasCX8 = 0;
cpu_features &= ~CPU_FEATURE_CX8;
if ((EAX & (1 << 20)) && models[model].cpu[cpu_manufacturer].cpus[cpu].cpu_type >= CPU_WINCHIP2)
cpu_has3DNOW = 1;
cpu_features |= CPU_FEATURE_3DNOW;
else
cpu_has3DNOW = 0;
cpu_features &= ~CPU_FEATURE_3DNOW;
if (EAX & (1 << 29))
CPUID = 0;
else

20
src/cpu.h
View file

@ -114,13 +114,19 @@ extern int cpu_multi;
/*Cyrix 5x86/6x86 only has data misalignment penalties when crossing 8-byte boundaries*/
extern int cpu_cyrix_alignment;
extern int cpu_hasrdtsc;
extern int cpu_hasMSR;
extern int cpu_hasMMX;
extern int cpu_hasCR4;
extern int cpu_hasVME;
extern int cpu_hasCX8;
extern int cpu_has3DNOW;
#define CPU_FEATURE_RDTSC (1 << 0)
#define CPU_FEATURE_MSR (1 << 1)
#define CPU_FEATURE_MMX (1 << 2)
#define CPU_FEATURE_CR4 (1 << 3)
#define CPU_FEATURE_VME (1 << 4)
#define CPU_FEATURE_CX8 (1 << 5)
#define CPU_FEATURE_3DNOW (1 << 6)
extern uint32_t cpu_features;
static int cpu_has_feature(int feature)
{
return cpu_features & feature;
}
#define CR4_TSD (1 << 2)
#define CR4_DE (1 << 3)

2
src/x86_ops_3dnow.h
View file

@ -19,7 +19,7 @@ static int opPREFETCH_a32(uint32_t fetchdat)
static int opFEMMS(uint32_t fetchdat)
{
ILLEGAL_ON(!cpu_hasMMX);
ILLEGAL_ON(!cpu_has_feature(CPU_FEATURE_MMX));
if (cr0 & 4)
{
x86_int(7);

4
src/x86_ops_misc.h
View file

@ -946,7 +946,7 @@ static int opCPUID(uint32_t fetchdat)
static int opRDMSR(uint32_t fetchdat)
{
if (cpu_hasMSR)
if (cpu_has_feature(CPU_FEATURE_MSR))
{
cpu_RDMSR();
CLOCK_CYCLES(9);
@ -959,7 +959,7 @@ static int opRDMSR(uint32_t fetchdat)
static int opWRMSR(uint32_t fetchdat)
{
if (cpu_hasMSR)
if (cpu_has_feature(CPU_FEATURE_MSR))
{
cpu_WRMSR();
CLOCK_CYCLES(9);

4
src/x86_ops_mmx.h
View file

@ -17,7 +17,7 @@
}
#define MMX_ENTER() \
if (!cpu_hasMMX) \
if (!cpu_has_feature(CPU_FEATURE_MMX)) \
{ \
cpu_state.pc = cpu_state.oldpc; \
x86illegal(); \
@ -32,7 +32,7 @@
static int opEMMS(uint32_t fetchdat)
{
if (!cpu_hasMMX)
if (!cpu_has_feature(CPU_FEATURE_MMX))
{
cpu_state.pc = cpu_state.oldpc;
x86illegal();

8
src/x86_ops_mov_ctrl.h
View file

@ -21,7 +21,7 @@ static int opMOV_r_CRx_a16(uint32_t fetchdat)
cpu_state.regs[cpu_rm].l = cr3;
break;
case 4:
if (cpu_hasCR4)
if (cpu_has_feature(CPU_FEATURE_CR4))
{
cpu_state.regs[cpu_rm].l = cr4;
break;
@ -59,7 +59,7 @@ static int opMOV_r_CRx_a32(uint32_t fetchdat)
cpu_state.regs[cpu_rm].l = cr3;
break;
case 4:
if (cpu_hasCR4)
if (cpu_has_feature(CPU_FEATURE_CR4))
{
cpu_state.regs[cpu_rm].l = cr4;
break;
@ -144,7 +144,7 @@ static int opMOV_CRx_r_a16(uint32_t fetchdat)
flushmmucache();
break;
case 4:
if (cpu_hasCR4)
if (cpu_has_feature(CPU_FEATURE_CR4))
{
cr4 = cpu_state.regs[cpu_rm].l & cpu_CR4_mask;
break;
@ -200,7 +200,7 @@ static int opMOV_CRx_r_a32(uint32_t fetchdat)
flushmmucache();
break;
case 4:
if (cpu_hasCR4)
if (cpu_has_feature(CPU_FEATURE_CR4))
{
cr4 = cpu_state.regs[cpu_rm].l & cpu_CR4_mask;
break;

2
src/x86_ops_msr.h
View file

@ -1,6 +1,6 @@
static int opRDTSC(uint32_t fetchdat)
{
if (!cpu_hasrdtsc)
if (!cpu_has_feature(CPU_FEATURE_RDTSC))
{
cpu_state.pc = cpu_state.oldpc;
x86illegal();