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Moved integer registers, PC and flags_* variables into new cpu_state structure. Reduces recompiled code size slightly, small speedup (1-3%).

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This commit is contained in:
SarahW 2016-04-20 21:39:41 +01:00
commit c81a91fd72
52 changed files with 1494 additions and 1408 deletions
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76
src/x86_ops_mov_ctrl.h
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@ -10,24 +10,25 @@ static int opMOV_r_CRx_a16(uint32_t fetchdat)
switch (reg)
{
case 0:
regs[rm].l = cr0;
if (is486) regs[rm].l |= 0x10; /*ET hardwired on 486*/
cpu_state.regs[rm].l = cr0;
if (is486)
cpu_state.regs[rm].l |= 0x10; /*ET hardwired on 486*/
break;
case 2:
regs[rm].l = cr2;
cpu_state.regs[rm].l = cr2;
break;
case 3:
regs[rm].l = cr3;
cpu_state.regs[rm].l = cr3;
break;
case 4:
if (cpu_hasCR4)
{
regs[rm].l = cr4;
cpu_state.regs[rm].l = cr4;
break;
}
default:
pclog("Bad read of CR%i %i\n",rmdat&7,reg);
pc = oldpc;
cpu_state.pc = oldpc;
x86illegal();
break;
}
@ -46,24 +47,25 @@ static int opMOV_r_CRx_a32(uint32_t fetchdat)
switch (reg)
{
case 0:
regs[rm].l = cr0;
if (is486) regs[rm].l |= 0x10; /*ET hardwired on 486*/
cpu_state.regs[rm].l = cr0;
if (is486)
cpu_state.regs[rm].l |= 0x10; /*ET hardwired on 486*/
break;
case 2:
regs[rm].l = cr2;
cpu_state.regs[rm].l = cr2;
break;
case 3:
regs[rm].l = cr3;
cpu_state.regs[rm].l = cr3;
break;
case 4:
if (cpu_hasCR4)
{
regs[rm].l = cr4;
cpu_state.regs[rm].l = cr4;
break;
}
default:
pclog("Bad read of CR%i %i\n",rmdat&7,reg);
pc = oldpc;
cpu_state.pc = oldpc;
x86illegal();
break;
}
@ -80,7 +82,7 @@ static int opMOV_r_DRx_a16(uint32_t fetchdat)
return 1;
}
fetch_ea_16(fetchdat);
regs[rm].l = dr[reg];
cpu_state.regs[rm].l = dr[reg];
CLOCK_CYCLES(6);
return 0;
}
@ -93,7 +95,7 @@ static int opMOV_r_DRx_a32(uint32_t fetchdat)
return 1;
}
fetch_ea_32(fetchdat);
regs[rm].l = dr[reg];
cpu_state.regs[rm].l = dr[reg];
CLOCK_CYCLES(6);
return 0;
}
@ -110,28 +112,31 @@ static int opMOV_CRx_r_a16(uint32_t fetchdat)
switch (reg)
{
case 0:
if ((regs[rm].l ^ cr0) & 0x80000001) flushmmucache();
cr0 = regs[rm].l;
if (cpu_16bitbus) cr0 |= 0x10;
if (!(cr0 & 0x80000000)) mmu_perm=4;
if ((cpu_state.regs[rm].l ^ cr0) & 0x80000001)
flushmmucache();
cr0 = cpu_state.regs[rm].l;
if (cpu_16bitbus)
cr0 |= 0x10;
if (!(cr0 & 0x80000000))
mmu_perm=4;
break;
case 2:
cr2 = regs[rm].l;
cr2 = cpu_state.regs[rm].l;
break;
case 3:
cr3 = regs[rm].l;
cr3 = cpu_state.regs[rm].l;
flushmmucache();
break;
case 4:
if (cpu_hasCR4)
{
cr4 = regs[rm].l & cpu_CR4_mask;
cr4 = cpu_state.regs[rm].l & cpu_CR4_mask;
break;
}
default:
pclog("Bad load CR%i\n", reg);
pc = oldpc;
cpu_state.pc = oldpc;
x86illegal();
break;
}
@ -150,28 +155,31 @@ static int opMOV_CRx_r_a32(uint32_t fetchdat)
switch (reg)
{
case 0:
if ((regs[rm].l ^ cr0) & 0x80000001) flushmmucache();
cr0 = regs[rm].l;
if (cpu_16bitbus) cr0 |= 0x10;
if (!(cr0 & 0x80000000)) mmu_perm=4;
if ((cpu_state.regs[rm].l ^ cr0) & 0x80000001)
flushmmucache();
cr0 = cpu_state.regs[rm].l;
if (cpu_16bitbus)
cr0 |= 0x10;
if (!(cr0 & 0x80000000))
mmu_perm=4;
break;
case 2:
cr2 = regs[rm].l;
cr2 = cpu_state.regs[rm].l;
break;
case 3:
cr3 = regs[rm].l;
cr3 = cpu_state.regs[rm].l;
flushmmucache();
break;
case 4:
if (cpu_hasCR4)
{
cr4 = regs[rm].l & cpu_CR4_mask;
cr4 = cpu_state.regs[rm].l & cpu_CR4_mask;
break;
}
default:
pclog("Bad load CR%i\n", reg);
pc = oldpc;
cpu_state.pc = oldpc;
x86illegal();
break;
}
@ -188,7 +196,7 @@ static int opMOV_DRx_r_a16(uint32_t fetchdat)
return 1;
}
fetch_ea_16(fetchdat);
dr[reg] = regs[rm].l;
dr[reg] = cpu_state.regs[rm].l;
CLOCK_CYCLES(6);
return 0;
}
@ -201,7 +209,7 @@ static int opMOV_DRx_r_a32(uint32_t fetchdat)
return 1;
}
fetch_ea_16(fetchdat);
dr[reg] = regs[rm].l;
dr[reg] = cpu_state.regs[rm].l;
CLOCK_CYCLES(6);
return 0;
}
@ -215,7 +223,7 @@ static int opMOV_r_TRx_a16(uint32_t fetchdat)
return 1;
}
fetch_ea_16(fetchdat);
regs[rm].l = 0;
cpu_state.regs[rm].l = 0;
CLOCK_CYCLES(6);
return 0;
}
@ -228,7 +236,7 @@ static int opMOV_r_TRx_a32(uint32_t fetchdat)
return 1;
}
fetch_ea_32(fetchdat);
regs[rm].l = 0;
cpu_state.regs[rm].l = 0;
CLOCK_CYCLES(6);
return 0;
}