Moved integer registers, PC and flags_* variables into new cpu_state structure. Reduces recompiled code size slightly, small speedup (1-3%).
This commit is contained in:
SarahW
parent
1fe6233d4c
commit
c81a91fd72
52 changed files with 1494 additions and 1408 deletions
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@ -6,11 +6,11 @@ static uint32_t ropINC_rw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
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host_reg = LOAD_REG_W(opcode & 7);
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STORE_HOST_REG_ADDR_WL((uint32_t)&flags_op1, host_reg);
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STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg);
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ADD_HOST_REG_IMM_W(host_reg, 1);
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STORE_IMM_ADDR_L((uint32_t)&flags_op2, 1);
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STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_INC16);
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STORE_HOST_REG_ADDR_WL((uint32_t)&flags_res, host_reg);
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STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, 1);
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STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_INC16);
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STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, host_reg);
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STORE_REG_W_RELEASE(host_reg);
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codegen_flags_changed = 1;
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@ -25,11 +25,11 @@ static uint32_t ropINC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
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host_reg = LOAD_REG_L(opcode & 7);
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STORE_HOST_REG_ADDR((uint32_t)&flags_op1, host_reg);
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STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg);
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ADD_HOST_REG_IMM(host_reg, 1);
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STORE_IMM_ADDR_L((uint32_t)&flags_op2, 1);
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STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_INC32);
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STORE_HOST_REG_ADDR((uint32_t)&flags_res, host_reg);
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STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, 1);
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STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_INC32);
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STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, host_reg);
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STORE_REG_L_RELEASE(host_reg);
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codegen_flags_changed = 1;
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@ -44,11 +44,11 @@ static uint32_t ropDEC_rw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
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host_reg = LOAD_REG_W(opcode & 7);
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STORE_HOST_REG_ADDR_WL((uint32_t)&flags_op1, host_reg);
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STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg);
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SUB_HOST_REG_IMM_W(host_reg, 1);
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STORE_IMM_ADDR_L((uint32_t)&flags_op2, 1);
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STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_DEC16);
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STORE_HOST_REG_ADDR_WL((uint32_t)&flags_res, host_reg);
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STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, 1);
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STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_DEC16);
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STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, host_reg);
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STORE_REG_W_RELEASE(host_reg);
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codegen_flags_changed = 1;
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@ -63,11 +63,11 @@ static uint32_t ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
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host_reg = LOAD_REG_L(opcode & 7);
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STORE_HOST_REG_ADDR((uint32_t)&flags_op1, host_reg);
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STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg);
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SUB_HOST_REG_IMM(host_reg, 1);
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STORE_IMM_ADDR_L((uint32_t)&flags_op2, 1);
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STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_DEC32);
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STORE_HOST_REG_ADDR((uint32_t)&flags_res, host_reg);
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STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, 1);
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STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_DEC32);
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STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, host_reg);
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STORE_REG_L_RELEASE(host_reg);
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codegen_flags_changed = 1;
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@ -84,12 +84,12 @@ static uint32_t ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
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return 0; \
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\
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dst_reg = LOAD_REG_B(fetchdat & 7); \
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STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ ## op ## 8); \
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STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ ## op ## 8); \
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src_reg = LOAD_REG_B((fetchdat >> 3) & 7); \
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STORE_HOST_REG_ADDR_BL((uint32_t)&flags_op1, dst_reg); \
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STORE_HOST_REG_ADDR_BL((uint32_t)&flags_op2, src_reg); \
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STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, dst_reg); \
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STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op2, src_reg); \
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op ## _HOST_REG_B(dst_reg, src_reg); \
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STORE_HOST_REG_ADDR_BL((uint32_t)&flags_res, dst_reg); \
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STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_res, dst_reg); \
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if (writeback) STORE_REG_B_RELEASE(dst_reg); \
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else RELEASE_REG(dst_reg); \
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RELEASE_REG(src_reg); \
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@ -105,12 +105,12 @@ static uint32_t ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
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return 0; \
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\
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dst_reg = LOAD_REG_W(fetchdat & 7); \
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STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ ## op ## 16); \
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STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ ## op ## 16); \
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src_reg = LOAD_REG_W((fetchdat >> 3) & 7); \
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STORE_HOST_REG_ADDR_WL((uint32_t)&flags_op1, dst_reg); \
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STORE_HOST_REG_ADDR_WL((uint32_t)&flags_op2, src_reg); \
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STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, dst_reg); \
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STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op2, src_reg); \
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op ## _HOST_REG_W(dst_reg, src_reg); \
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STORE_HOST_REG_ADDR_WL((uint32_t)&flags_res, dst_reg); \
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STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, dst_reg); \
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if (writeback) STORE_REG_W_RELEASE(dst_reg); \
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else RELEASE_REG(dst_reg); \
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RELEASE_REG(src_reg); \
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@ -126,12 +126,12 @@ static uint32_t ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
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return 0; \
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\
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dst_reg = LOAD_REG_L(fetchdat & 7); \
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STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ ## op ## 32); \
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STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ ## op ## 32); \
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src_reg = LOAD_REG_L((fetchdat >> 3) & 7); \
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STORE_HOST_REG_ADDR((uint32_t)&flags_op1, dst_reg); \
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STORE_HOST_REG_ADDR((uint32_t)&flags_op2, src_reg); \
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STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, dst_reg); \
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STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op2, src_reg); \
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op ## _HOST_REG_L(dst_reg, src_reg); \
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STORE_HOST_REG_ADDR((uint32_t)&flags_res, dst_reg); \
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STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, dst_reg); \
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if (writeback) STORE_REG_L_RELEASE(dst_reg); \
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else RELEASE_REG(dst_reg); \
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RELEASE_REG(src_reg); \
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@ -158,11 +158,11 @@ static uint32_t ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
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} \
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\
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dst_reg = LOAD_REG_B((fetchdat >> 3) & 7); \
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STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ ## op ## 8); \
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STORE_HOST_REG_ADDR_BL((uint32_t)&flags_op1, dst_reg); \
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STORE_HOST_REG_ADDR_BL((uint32_t)&flags_op2, src_reg); \
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STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ ## op ## 8); \
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STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, dst_reg); \
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STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op2, src_reg); \
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op ## _HOST_REG_B(dst_reg, src_reg); \
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STORE_HOST_REG_ADDR_BL((uint32_t)&flags_res, dst_reg); \
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STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_res, dst_reg); \
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if (writeback) STORE_REG_B_RELEASE(dst_reg); \
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else RELEASE_REG(dst_reg); \
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RELEASE_REG(src_reg); \
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@ -187,11 +187,11 @@ static uint32_t ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
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} \
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\
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dst_reg = LOAD_REG_W((fetchdat >> 3) & 7); \
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STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ ## op ## 16); \
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STORE_HOST_REG_ADDR_WL((uint32_t)&flags_op1, dst_reg); \
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STORE_HOST_REG_ADDR_WL((uint32_t)&flags_op2, src_reg); \
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STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ ## op ## 16); \
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STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, dst_reg); \
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STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op2, src_reg); \
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op ## _HOST_REG_W(dst_reg, src_reg); \
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STORE_HOST_REG_ADDR_WL((uint32_t)&flags_res, dst_reg); \
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STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, dst_reg); \
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if (writeback) STORE_REG_W_RELEASE(dst_reg); \
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else RELEASE_REG(dst_reg); \
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RELEASE_REG(src_reg); \
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@ -216,11 +216,11 @@ static uint32_t ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
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} \
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\
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dst_reg = LOAD_REG_L((fetchdat >> 3) & 7); \
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STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ ## op ## 32); \
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STORE_HOST_REG_ADDR((uint32_t)&flags_op1, dst_reg); \
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STORE_HOST_REG_ADDR((uint32_t)&flags_op2, src_reg); \
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STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ ## op ## 32); \
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STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, dst_reg); \
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STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op2, src_reg); \
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op ## _HOST_REG_L(dst_reg, src_reg); \
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STORE_HOST_REG_ADDR((uint32_t)&flags_res, dst_reg); \
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STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, dst_reg); \
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if (writeback) STORE_REG_L_RELEASE(dst_reg); \
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else RELEASE_REG(dst_reg); \
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RELEASE_REG(src_reg); \
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@ -251,11 +251,11 @@ static uint32_t ropCMP_b_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
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}
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dst_reg = LOAD_REG_B((fetchdat >> 3) & 7);
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STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB8);
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STORE_HOST_REG_ADDR_BL((uint32_t)&flags_op1, dst_reg);
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STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB8);
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STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, dst_reg);
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dst_reg = CMP_HOST_REG_B(dst_reg, src_reg);
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STORE_HOST_REG_ADDR_BL((uint32_t)&flags_op2, src_reg);
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STORE_HOST_REG_ADDR_BL((uint32_t)&flags_res, dst_reg);
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STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op2, src_reg);
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STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_res, dst_reg);
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RELEASE_REG(dst_reg);
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RELEASE_REG(src_reg);
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@ -279,11 +279,11 @@ static uint32_t ropCMP_w_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
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}
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dst_reg = LOAD_REG_W((fetchdat >> 3) & 7);
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STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB16);
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STORE_HOST_REG_ADDR_WL((uint32_t)&flags_op1, dst_reg);
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STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB16);
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STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, dst_reg);
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dst_reg = CMP_HOST_REG_W(dst_reg, src_reg);
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STORE_HOST_REG_ADDR_WL((uint32_t)&flags_op2, src_reg);
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STORE_HOST_REG_ADDR_WL((uint32_t)&flags_res, dst_reg);
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STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op2, src_reg);
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STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, dst_reg);
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RELEASE_REG(dst_reg);
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RELEASE_REG(src_reg);
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@ -307,11 +307,11 @@ static uint32_t ropCMP_l_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
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}
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dst_reg = LOAD_REG_L((fetchdat >> 3) & 7);
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STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB32);
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STORE_HOST_REG_ADDR((uint32_t)&flags_op1, dst_reg);
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STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB32);
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STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, dst_reg);
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dst_reg = CMP_HOST_REG_L(dst_reg, src_reg);
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STORE_HOST_REG_ADDR((uint32_t)&flags_op2, src_reg);
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STORE_HOST_REG_ADDR((uint32_t)&flags_res, dst_reg);
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STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op2, src_reg);
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STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, dst_reg);
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RELEASE_REG(dst_reg);
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RELEASE_REG(src_reg);
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@ -335,12 +335,12 @@ static uint32_t ropCMP_b_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
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dst_reg = 0;
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}
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STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB8);
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STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB8);
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src_reg = LOAD_REG_B((fetchdat >> 3) & 7);
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STORE_HOST_REG_ADDR_BL((uint32_t)&flags_op1, dst_reg);
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STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, dst_reg);
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dst_reg = CMP_HOST_REG_B(dst_reg, src_reg);
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STORE_HOST_REG_ADDR_BL((uint32_t)&flags_op2, src_reg);
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STORE_HOST_REG_ADDR_BL((uint32_t)&flags_res, dst_reg);
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STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op2, src_reg);
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STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_res, dst_reg);
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RELEASE_REG(dst_reg);
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RELEASE_REG(src_reg);
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@ -363,12 +363,12 @@ static uint32_t ropCMP_w_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
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dst_reg = 0;
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} \
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STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB16);
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STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB16);
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src_reg = LOAD_REG_W((fetchdat >> 3) & 7);
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STORE_HOST_REG_ADDR_WL((uint32_t)&flags_op1, dst_reg);
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STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, dst_reg);
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dst_reg = CMP_HOST_REG_W(dst_reg, src_reg);
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STORE_HOST_REG_ADDR_WL((uint32_t)&flags_op2, src_reg);
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STORE_HOST_REG_ADDR_WL((uint32_t)&flags_res, dst_reg);
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STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op2, src_reg);
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STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, dst_reg);
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RELEASE_REG(dst_reg);
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RELEASE_REG(src_reg);
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@ -391,12 +391,12 @@ static uint32_t ropCMP_l_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
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dst_reg = 0;
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}
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STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB32);
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STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB32);
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src_reg = LOAD_REG_L((fetchdat >> 3) & 7);
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STORE_HOST_REG_ADDR((uint32_t)&flags_op1, dst_reg);
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STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, dst_reg);
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dst_reg = CMP_HOST_REG_L(dst_reg, src_reg);
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STORE_HOST_REG_ADDR((uint32_t)&flags_op2, src_reg);
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STORE_HOST_REG_ADDR((uint32_t)&flags_res, dst_reg);
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STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op2, src_reg);
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STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, dst_reg);
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RELEASE_REG(dst_reg);
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RELEASE_REG(src_reg);
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@ -409,11 +409,11 @@ static uint32_t ropADD_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
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{
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int host_reg = LOAD_REG_B(REG_AL);
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STORE_HOST_REG_ADDR_BL((uint32_t)&flags_op1, host_reg);
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STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, host_reg);
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ADD_HOST_REG_IMM_B(host_reg, fetchdat & 0xff);
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STORE_IMM_ADDR_L((uint32_t)&flags_op2, fetchdat & 0xff);
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STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ADD8);
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STORE_HOST_REG_ADDR_BL((uint32_t)&flags_res, host_reg);
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STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, fetchdat & 0xff);
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STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ADD8);
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STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_res, host_reg);
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STORE_REG_B_RELEASE(host_reg);
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||||
|
||||
codegen_flags_changed = 1;
|
||||
|
|
@ -423,11 +423,11 @@ static uint32_t ropADD_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
|
|||
{
|
||||
int host_reg = LOAD_REG_W(REG_AX);
|
||||
|
||||
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_op1, host_reg);
|
||||
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg);
|
||||
ADD_HOST_REG_IMM_W(host_reg, fetchdat & 0xffff);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op2, fetchdat & 0xffff);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ADD16);
|
||||
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_res, host_reg);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, fetchdat & 0xffff);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ADD16);
|
||||
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, host_reg);
|
||||
STORE_REG_W_RELEASE(host_reg);
|
||||
|
||||
codegen_flags_changed = 1;
|
||||
|
|
@ -437,12 +437,12 @@ static uint32_t ropADD_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32
|
|||
{
|
||||
int host_reg = LOAD_REG_L(REG_EAX);
|
||||
|
||||
STORE_HOST_REG_ADDR((uint32_t)&flags_op1, host_reg);
|
||||
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg);
|
||||
fetchdat = fastreadl(cs + op_pc);
|
||||
ADD_HOST_REG_IMM(host_reg, fetchdat);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op2, fetchdat);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ADD32);
|
||||
STORE_HOST_REG_ADDR((uint32_t)&flags_res, host_reg);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, fetchdat);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ADD32);
|
||||
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, host_reg);
|
||||
STORE_REG_L_RELEASE(host_reg);
|
||||
|
||||
codegen_flags_changed = 1;
|
||||
|
|
@ -453,11 +453,11 @@ static uint32_t ropCMP_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
|
|||
{
|
||||
int host_reg = LOAD_REG_B(REG_AL);
|
||||
|
||||
STORE_HOST_REG_ADDR_BL((uint32_t)&flags_op1, host_reg);
|
||||
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, host_reg);
|
||||
host_reg = CMP_HOST_REG_IMM_B(host_reg, fetchdat & 0xff);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op2, fetchdat & 0xff);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB8);
|
||||
STORE_HOST_REG_ADDR_BL((uint32_t)&flags_res, host_reg);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, fetchdat & 0xff);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB8);
|
||||
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_res, host_reg);
|
||||
RELEASE_REG(host_reg);
|
||||
|
||||
codegen_flags_changed = 1;
|
||||
|
|
@ -467,11 +467,11 @@ static uint32_t ropCMP_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
|
|||
{
|
||||
int host_reg = LOAD_REG_W(REG_AX);
|
||||
|
||||
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_op1, host_reg);
|
||||
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg);
|
||||
host_reg = CMP_HOST_REG_IMM_W(host_reg, fetchdat & 0xffff);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op2, fetchdat & 0xffff);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB16);
|
||||
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_res, host_reg);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, fetchdat & 0xffff);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB16);
|
||||
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, host_reg);
|
||||
RELEASE_REG(host_reg);
|
||||
|
||||
codegen_flags_changed = 1;
|
||||
|
|
@ -481,12 +481,12 @@ static uint32_t ropCMP_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32
|
|||
{
|
||||
int host_reg = LOAD_REG_L(REG_EAX);
|
||||
|
||||
STORE_HOST_REG_ADDR((uint32_t)&flags_op1, host_reg);
|
||||
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg);
|
||||
fetchdat = fastreadl(cs + op_pc);
|
||||
host_reg = CMP_HOST_REG_IMM_L(host_reg, fetchdat);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op2, fetchdat);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB32);
|
||||
STORE_HOST_REG_ADDR((uint32_t)&flags_res, host_reg);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, fetchdat);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB32);
|
||||
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, host_reg);
|
||||
RELEASE_REG(host_reg);
|
||||
|
||||
codegen_flags_changed = 1;
|
||||
|
|
@ -497,11 +497,11 @@ static uint32_t ropSUB_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
|
|||
{
|
||||
int host_reg = LOAD_REG_B(REG_AL);
|
||||
|
||||
STORE_HOST_REG_ADDR_BL((uint32_t)&flags_op1, host_reg);
|
||||
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, host_reg);
|
||||
SUB_HOST_REG_IMM_B(host_reg, fetchdat & 0xff);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op2, fetchdat & 0xff);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB8);
|
||||
STORE_HOST_REG_ADDR_BL((uint32_t)&flags_res, host_reg);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, fetchdat & 0xff);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB8);
|
||||
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_res, host_reg);
|
||||
STORE_REG_B_RELEASE(host_reg);
|
||||
|
||||
codegen_flags_changed = 1;
|
||||
|
|
@ -511,11 +511,11 @@ static uint32_t ropSUB_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
|
|||
{
|
||||
int host_reg = LOAD_REG_W(REG_AX);
|
||||
|
||||
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_op1, host_reg);
|
||||
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg);
|
||||
SUB_HOST_REG_IMM_W(host_reg, fetchdat & 0xffff);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op2, fetchdat & 0xffff);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB16);
|
||||
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_res, host_reg);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, fetchdat & 0xffff);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB16);
|
||||
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, host_reg);
|
||||
STORE_REG_W_RELEASE(host_reg);
|
||||
|
||||
codegen_flags_changed = 1;
|
||||
|
|
@ -525,12 +525,12 @@ static uint32_t ropSUB_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32
|
|||
{
|
||||
int host_reg = LOAD_REG_L(REG_EAX);
|
||||
|
||||
STORE_HOST_REG_ADDR((uint32_t)&flags_op1, host_reg);
|
||||
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg);
|
||||
fetchdat = fastreadl(cs + op_pc);
|
||||
SUB_HOST_REG_IMM(host_reg, fetchdat);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op2, fetchdat);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB32);
|
||||
STORE_HOST_REG_ADDR((uint32_t)&flags_res, host_reg);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, fetchdat);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB32);
|
||||
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, host_reg);
|
||||
STORE_REG_L_RELEASE(host_reg);
|
||||
|
||||
codegen_flags_changed = 1;
|
||||
|
|
@ -551,38 +551,38 @@ static uint32_t rop80(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_
|
|||
switch (fetchdat & 0x38)
|
||||
{
|
||||
case 0x00: /*ADD*/
|
||||
STORE_HOST_REG_ADDR_BL((uint32_t)&flags_op1, host_reg);
|
||||
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, host_reg);
|
||||
ADD_HOST_REG_IMM_B(host_reg, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op2, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ADD8);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ADD8);
|
||||
break;
|
||||
case 0x08: /*OR*/
|
||||
OR_HOST_REG_IMM(host_reg, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ZN8);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN8);
|
||||
break;
|
||||
case 0x20: /*AND*/
|
||||
AND_HOST_REG_IMM(host_reg, imm | 0xffffff00);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ZN8);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN8);
|
||||
break;
|
||||
case 0x28: /*SUB*/
|
||||
STORE_HOST_REG_ADDR_BL((uint32_t)&flags_op1, host_reg);
|
||||
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, host_reg);
|
||||
SUB_HOST_REG_IMM_B(host_reg, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op2, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB8);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB8);
|
||||
break;
|
||||
case 0x30: /*XOR*/
|
||||
XOR_HOST_REG_IMM(host_reg, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ZN8);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN8);
|
||||
break;
|
||||
case 0x38: /*CMP*/
|
||||
STORE_HOST_REG_ADDR_BL((uint32_t)&flags_op1, host_reg);
|
||||
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, host_reg);
|
||||
host_reg = CMP_HOST_REG_IMM_B(host_reg, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op2, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB8);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB8);
|
||||
break;
|
||||
}
|
||||
|
||||
STORE_HOST_REG_ADDR_BL((uint32_t)&flags_res, host_reg);
|
||||
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_res, host_reg);
|
||||
if ((fetchdat & 0x38) != 0x38)
|
||||
STORE_REG_B_RELEASE(host_reg);
|
||||
else
|
||||
|
|
@ -606,38 +606,38 @@ static uint32_t rop81_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
|
|||
switch (fetchdat & 0x38)
|
||||
{
|
||||
case 0x00: /*ADD*/
|
||||
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_op1, host_reg);
|
||||
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg);
|
||||
ADD_HOST_REG_IMM_W(host_reg, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op2, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ADD16);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ADD16);
|
||||
break;
|
||||
case 0x08: /*OR*/
|
||||
OR_HOST_REG_IMM(host_reg, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ZN16);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN16);
|
||||
break;
|
||||
case 0x20: /*AND*/
|
||||
AND_HOST_REG_IMM(host_reg, imm | 0xffff0000);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ZN16);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN16);
|
||||
break;
|
||||
case 0x28: /*SUB*/
|
||||
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_op1, host_reg);
|
||||
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg);
|
||||
SUB_HOST_REG_IMM_W(host_reg, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op2, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB16);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB16);
|
||||
break;
|
||||
case 0x30: /*XOR*/
|
||||
XOR_HOST_REG_IMM(host_reg, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ZN16);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN16);
|
||||
break;
|
||||
case 0x38: /*CMP*/
|
||||
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_op1, host_reg);
|
||||
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg);
|
||||
host_reg = CMP_HOST_REG_IMM_W(host_reg, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op2, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB16);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB16);
|
||||
break;
|
||||
}
|
||||
|
||||
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_res, host_reg);
|
||||
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, host_reg);
|
||||
if ((fetchdat & 0x38) != 0x38)
|
||||
STORE_REG_W_RELEASE(host_reg);
|
||||
else
|
||||
|
|
@ -661,38 +661,38 @@ static uint32_t rop81_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
|
|||
switch (fetchdat & 0x38)
|
||||
{
|
||||
case 0x00: /*ADD*/
|
||||
STORE_HOST_REG_ADDR((uint32_t)&flags_op1, host_reg);
|
||||
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg);
|
||||
ADD_HOST_REG_IMM(host_reg, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op2, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ADD32);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ADD32);
|
||||
break;
|
||||
case 0x08: /*OR*/
|
||||
OR_HOST_REG_IMM(host_reg, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ZN32);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN32);
|
||||
break;
|
||||
case 0x20: /*AND*/
|
||||
AND_HOST_REG_IMM(host_reg, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ZN32);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN32);
|
||||
break;
|
||||
case 0x28: /*SUB*/
|
||||
STORE_HOST_REG_ADDR((uint32_t)&flags_op1, host_reg);
|
||||
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg);
|
||||
SUB_HOST_REG_IMM(host_reg, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op2, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB32);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB32);
|
||||
break;
|
||||
case 0x30: /*XOR*/
|
||||
XOR_HOST_REG_IMM(host_reg, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ZN32);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN32);
|
||||
break;
|
||||
case 0x38: /*CMP*/
|
||||
STORE_HOST_REG_ADDR((uint32_t)&flags_op1, host_reg);
|
||||
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg);
|
||||
host_reg = CMP_HOST_REG_IMM_L(host_reg, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op2, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB32);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB32);
|
||||
break;
|
||||
}
|
||||
|
||||
STORE_HOST_REG_ADDR((uint32_t)&flags_res, host_reg);
|
||||
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, host_reg);
|
||||
if ((fetchdat & 0x38) != 0x38)
|
||||
STORE_REG_L_RELEASE(host_reg);
|
||||
else
|
||||
|
|
@ -718,38 +718,38 @@ static uint32_t rop83_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
|
|||
switch (fetchdat & 0x38)
|
||||
{
|
||||
case 0x00: /*ADD*/
|
||||
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_op1, host_reg);
|
||||
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg);
|
||||
ADD_HOST_REG_IMM_W(host_reg, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op2, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ADD16);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ADD16);
|
||||
break;
|
||||
case 0x08: /*OR*/
|
||||
OR_HOST_REG_IMM(host_reg, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ZN16);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN16);
|
||||
break;
|
||||
case 0x20: /*AND*/
|
||||
AND_HOST_REG_IMM(host_reg, imm | 0xffff0000);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ZN16);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN16);
|
||||
break;
|
||||
case 0x28: /*SUB*/
|
||||
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_op1, host_reg);
|
||||
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg);
|
||||
SUB_HOST_REG_IMM_W(host_reg, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op2, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB16);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB16);
|
||||
break;
|
||||
case 0x30: /*XOR*/
|
||||
XOR_HOST_REG_IMM(host_reg, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ZN16);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN16);
|
||||
break;
|
||||
case 0x38: /*CMP*/
|
||||
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_op1, host_reg);
|
||||
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg);
|
||||
host_reg = CMP_HOST_REG_IMM_W(host_reg, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op2, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB16);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB16);
|
||||
break;
|
||||
}
|
||||
|
||||
STORE_HOST_REG_ADDR_WL((uint32_t)&flags_res, host_reg);
|
||||
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, host_reg);
|
||||
if ((fetchdat & 0x38) != 0x38)
|
||||
STORE_REG_W_RELEASE(host_reg);
|
||||
else
|
||||
|
|
@ -774,38 +774,38 @@ static uint32_t rop83_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
|
|||
switch (fetchdat & 0x38)
|
||||
{
|
||||
case 0x00: /*ADD*/
|
||||
STORE_HOST_REG_ADDR((uint32_t)&flags_op1, host_reg);
|
||||
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg);
|
||||
ADD_HOST_REG_IMM(host_reg, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op2, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ADD32);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ADD32);
|
||||
break;
|
||||
case 0x08: /*OR*/
|
||||
OR_HOST_REG_IMM(host_reg, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ZN32);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN32);
|
||||
break;
|
||||
case 0x20: /*AND*/
|
||||
AND_HOST_REG_IMM(host_reg, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ZN32);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN32);
|
||||
break;
|
||||
case 0x28: /*SUB*/
|
||||
STORE_HOST_REG_ADDR((uint32_t)&flags_op1, host_reg);
|
||||
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg);
|
||||
SUB_HOST_REG_IMM(host_reg, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op2, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB32);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB32);
|
||||
break;
|
||||
case 0x30: /*XOR*/
|
||||
XOR_HOST_REG_IMM(host_reg, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_ZN32);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN32);
|
||||
break;
|
||||
case 0x38: /*CMP*/
|
||||
STORE_HOST_REG_ADDR((uint32_t)&flags_op1, host_reg);
|
||||
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg);
|
||||
host_reg = CMP_HOST_REG_IMM_L(host_reg, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op2, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&flags_op, FLAGS_SUB32);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
|
||||
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB32);
|
||||
break;
|
||||
}
|
||||
|
||||
STORE_HOST_REG_ADDR((uint32_t)&flags_res, host_reg);
|
||||
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, host_reg);
|
||||
if ((fetchdat & 0x38) != 0x38)
|
||||
STORE_REG_L_RELEASE(host_reg);
|
||||
else
|
||||
|
|
|
|||
Loading…
Reference in a new issue