Fix partial register handling - removes pointless loads when writing to non-32-bit registers (eg FPU or MMX).
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2 changed files with 34 additions and 5 deletions
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@ -37,7 +37,7 @@ enum
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IREG_eaaddr = 14,
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IREG_ea_seg = 15,
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IREG_op32 = 16,
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IREG_ssegs = 17,
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IREG_ssegsx = 17,
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IREG_rm_mod_reg = 18,
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@ -179,7 +179,9 @@ enum
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IREG_MM7 = IREG_MM7x + IREG_SIZE_Q,
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IREG_NPXC = IREG_NPXCx + IREG_SIZE_W,
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IREG_NPXS = IREG_NPXSx + IREG_SIZE_W
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IREG_NPXS = IREG_NPXSx + IREG_SIZE_W,
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IREG_ssegs = IREG_ssegsx + IREG_SIZE_B
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};
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#define IREG_8(reg) (((reg) & 4) ? (((reg) & 3) + IREG_AH) : ((reg) + IREG_AL))
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