Added recompiled versions of FFREE, FLD, FST, FSTP and FXCH.
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6d8af5df4a
commit
bce9ad4f3d
12 changed files with 364 additions and 27 deletions
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@ -18,6 +18,7 @@
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#define REG_IS_B(size) (size == IREG_SIZE_B)
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#define REG_IS_BH(size) (size == IREG_SIZE_BH)
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#define REG_IS_D(size) (size == IREG_SIZE_D)
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#define REG_IS_Q(size) (size == IREG_SIZE_Q)
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static int codegen_ADD(codeblock_t *block, uop_t *uop)
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{
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@ -1040,6 +1041,14 @@ static int codegen_MOV(codeblock_t *block, uop_t *uop)
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host_arm64_MOV_REG_LSR(block, REG_TEMP, src_reg, 8);
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host_arm64_BFI(block, dest_reg, REG_TEMP, 8, 8);
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}
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else if (REG_IS_D(dest_size) && REG_IS_D(src_size))
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{
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host_arm64_FMOV_D_D(block, dest_reg, src_reg);
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}
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else if (REG_IS_Q(dest_size) && REG_IS_Q(src_size))
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{
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host_arm64_FMOV_D_D(block, dest_reg, src_reg);
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}
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else
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fatal("MOV %x %x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
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@ -1767,6 +1776,13 @@ void codegen_direct_read_32(codeblock_t *block, int host_reg, void *p)
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else
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fatal("codegen_direct_read_32 - not in range\n");
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}
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void codegen_direct_read_64(codeblock_t *block, int host_reg, void *p)
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{
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if (in_range12_q((uintptr_t)p - (uintptr_t)&cpu_state))
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host_arm64_LDR_IMM_F64(block, host_reg, REG_CPUSTATE, (uintptr_t)p - (uintptr_t)&cpu_state);
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else
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fatal("codegen_direct_read_double - not in range\n");
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}
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void codegen_direct_read_double(codeblock_t *block, int host_reg, void *p)
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{
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if (in_range12_q((uintptr_t)p - (uintptr_t)&cpu_state))
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@ -1774,6 +1790,22 @@ void codegen_direct_read_double(codeblock_t *block, int host_reg, void *p)
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else
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fatal("codegen_direct_read_double - not in range\n");
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}
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void codegen_direct_read_st_8(codeblock_t *block, int host_reg, void *base, int reg_idx)
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{
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host_arm64_LDR_IMM_W(block, REG_TEMP, REG_SP, IREG_TOP_diff_stack_offset);
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host_arm64_ADD_IMM(block, REG_TEMP, REG_TEMP, reg_idx);
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host_arm64_ADD_IMM(block, REG_TEMP2, REG_CPUSTATE, (uintptr_t)base - (uintptr_t)&cpu_state);
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host_arm64_AND_IMM(block, REG_TEMP, REG_TEMP, 7);
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host_arm64_LDRB_REG(block, host_reg, REG_TEMP2, REG_TEMP);
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}
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void codegen_direct_read_st_64(codeblock_t *block, int host_reg, void *base, int reg_idx)
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{
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host_arm64_LDR_IMM_W(block, REG_TEMP, REG_SP, IREG_TOP_diff_stack_offset);
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host_arm64_ADD_IMM(block, REG_TEMP, REG_TEMP, reg_idx);
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host_arm64_ADD_IMM(block, REG_TEMP2, REG_CPUSTATE, (uintptr_t)base - (uintptr_t)&cpu_state);
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host_arm64_AND_IMM(block, REG_TEMP, REG_TEMP, 7);
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host_arm64_LDR_REG_F64_S(block, host_reg, REG_TEMP2, REG_TEMP);
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}
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void codegen_direct_read_st_double(codeblock_t *block, int host_reg, void *base, int reg_idx)
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{
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host_arm64_LDR_IMM_W(block, REG_TEMP, REG_SP, IREG_TOP_diff_stack_offset);
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@ -1804,6 +1836,20 @@ void codegen_direct_write_32(codeblock_t *block, void *p, int host_reg)
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else
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fatal("codegen_direct_write_32 - not in range\n");
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}
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void codegen_direct_write_64(codeblock_t *block, void *p, int host_reg)
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{
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if (in_range12_q((uintptr_t)p - (uintptr_t)&cpu_state))
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host_arm64_STR_IMM_F64(block, host_reg, REG_CPUSTATE, (uintptr_t)p - (uintptr_t)&cpu_state);
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else
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fatal("codegen_direct_write_double - not in range\n");
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}
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void codegen_direct_write_double(codeblock_t *block, void *p, int host_reg)
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{
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if (in_range12_q((uintptr_t)p - (uintptr_t)&cpu_state))
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host_arm64_STR_IMM_F64(block, host_reg, REG_CPUSTATE, (uintptr_t)p - (uintptr_t)&cpu_state);
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else
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fatal("codegen_direct_write_double - not in range\n");
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}
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void codegen_direct_write_st_8(codeblock_t *block, void *base, int reg_idx, int host_reg)
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{
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host_arm64_LDR_IMM_W(block, REG_TEMP, REG_SP, IREG_TOP_diff_stack_offset);
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@ -1812,12 +1858,13 @@ void codegen_direct_write_st_8(codeblock_t *block, void *base, int reg_idx, int
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host_arm64_AND_IMM(block, REG_TEMP, REG_TEMP, 7);
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host_arm64_STRB_REG(block, host_reg, REG_TEMP2, REG_TEMP);
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}
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void codegen_direct_write_double(codeblock_t *block, void *p, int host_reg)
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void codegen_direct_write_st_64(codeblock_t *block, void *base, int reg_idx, int host_reg)
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{
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if (in_range12_q((uintptr_t)p - (uintptr_t)&cpu_state))
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host_arm64_STR_IMM_F64(block, host_reg, REG_CPUSTATE, (uintptr_t)p - (uintptr_t)&cpu_state);
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else
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fatal("codegen_direct_write_double - not in range\n");
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host_arm64_LDR_IMM_W(block, REG_TEMP, REG_SP, IREG_TOP_diff_stack_offset);
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host_arm64_ADD_IMM(block, REG_TEMP, REG_TEMP, reg_idx);
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host_arm64_ADD_IMM(block, REG_TEMP2, REG_CPUSTATE, (uintptr_t)base - (uintptr_t)&cpu_state);
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host_arm64_AND_IMM(block, REG_TEMP, REG_TEMP, 7);
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host_arm64_STR_REG_F64_S(block, host_reg, REG_TEMP2, REG_TEMP);
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}
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void codegen_direct_write_st_double(codeblock_t *block, void *base, int reg_idx, int host_reg)
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{
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