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Rewrote timer code.

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The new code is based on timestamps, rather than delays. This eliminates the
need to update every timer in timer_process(), which cost a non-trivial amount
of CPU time on low-end machines.

This involved changes to every user of the timer code, so this change almost
certainly introduces bugs.
This commit is contained in:
SarahW 2018-08-02 22:06:10 +01:00
commit a7d006b637
79 changed files with 1050 additions and 1033 deletions
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13
src/vid_tandysl.c
View file

@ -35,7 +35,8 @@ typedef struct tandysl_t
int vsynctime, vadj;
uint16_t ma, maback;
int dispontime, dispofftime, vidtime;
uint64_t dispontime, dispofftime;
pc_timer_t timer;
int firstline, lastline;
} tandysl_t;
@ -249,8 +250,8 @@ static void tandysl_recalctimings(tandysl_t *tandy)
_dispofftime = disptime - _dispontime;
_dispontime *= CGACONST;
_dispofftime *= CGACONST;
tandy->dispontime = (int)(_dispontime * (1 << TIMER_SHIFT));
tandy->dispofftime = (int)(_dispofftime * (1 << TIMER_SHIFT));
tandy->dispontime = (uint64_t)_dispontime;
tandy->dispofftime = (uint64_t)_dispofftime;
}
@ -272,7 +273,7 @@ static void tandysl_poll(void *p)
// pclog("tandy_poll vc=%i sc=%i dispon=%i\n", tandy->vc, tandy->sc, tandy->dispon);
// cgapal[0]=tandy->col&15;
// printf("Firstline %i Lastline %i tandy->displine %i\n",firstline,lastline,tandy->displine);
tandy->vidtime += tandy->dispofftime;
timer_advance_u64(&tandy->timer, tandy->dispofftime);
tandy->stat |= 1;
tandy->linepos = 1;
oldsc = tandy->sc;
@ -537,7 +538,7 @@ static void tandysl_poll(void *p)
}
else
{
tandy->vidtime += tandy->dispontime;
timer_advance_u64(&tandy->timer, tandy->dispontime);
if (tandy->dispon)
tandy->stat &= ~1;
tandy->linepos = 0;
@ -694,7 +695,7 @@ static void *tandysl_init()
tandy->b8000_limit = 0x8000;
tandy->planar_ctrl = 4;
timer_add(tandysl_poll, &tandy->vidtime, TIMER_ALWAYS_ENABLED, tandy);
timer_add(&tandy->timer, tandysl_poll, tandy, 1);
mem_mapping_add(&tandy->mapping, 0xb8000, 0x08000, tandysl_read, NULL, NULL, tandysl_write, NULL, NULL, NULL, 0, tandy);
mem_mapping_add(&tandy->ram_mapping, 0x80000, 0x20000, tandysl_ram_read, NULL, NULL, tandysl_ram_write, NULL, NULL, NULL, 0, tandy);
/*Base 128k mapping is controlled via port 0xffe8, so we remove it from the main mapping*/