Move flags and eflags variables into cpu_struct.
This commit is contained in:
SarahW
parent
c1565eb42f
commit
a4d3aa1912
25 changed files with 1013 additions and 958 deletions
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@ -13,9 +13,9 @@
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c--; \
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} \
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seteab(temp); if (cpu_state.abrt) return 1; \
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flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) flags |= C_FLAG; \
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if ((flags & C_FLAG) ^ (temp >> 7)) flags |= V_FLAG; \
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cpu_state.flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) cpu_state.flags |= C_FLAG; \
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if ((cpu_state.flags & C_FLAG) ^ (temp >> 7)) cpu_state.flags |= V_FLAG; \
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
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PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
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break; \
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@ -28,14 +28,14 @@
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c--; \
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} \
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seteab(temp); if (cpu_state.abrt) return 1; \
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flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) flags |= C_FLAG; \
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if ((temp ^ (temp >> 1)) & 0x40) flags |= V_FLAG; \
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cpu_state.flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) cpu_state.flags |= C_FLAG; \
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if ((temp ^ (temp >> 1)) & 0x40) cpu_state.flags |= V_FLAG; \
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
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PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
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break; \
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case 0x10: /*RCL b,CL*/ \
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temp2 = flags & C_FLAG; \
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temp2 = cpu_state.flags & C_FLAG; \
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if (is486) CLOCK_CYCLES_ALWAYS(c); \
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while (c > 0) \
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{ \
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@ -45,14 +45,14 @@
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c--; \
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} \
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seteab(temp); if (cpu_state.abrt) return 1; \
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flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) flags |= C_FLAG; \
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if ((flags & C_FLAG) ^ (temp >> 7)) flags |= V_FLAG; \
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cpu_state.flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) cpu_state.flags |= C_FLAG; \
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if ((cpu_state.flags & C_FLAG) ^ (temp >> 7)) cpu_state.flags |= V_FLAG; \
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CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
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PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
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break; \
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case 0x18: /*RCR b,CL*/ \
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temp2 = flags & C_FLAG; \
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temp2 = cpu_state.flags & C_FLAG; \
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if (is486) CLOCK_CYCLES_ALWAYS(c); \
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while (c > 0) \
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{ \
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@ -62,9 +62,9 @@
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c--; \
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} \
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seteab(temp); if (cpu_state.abrt) return 1; \
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flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) flags |= C_FLAG; \
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if ((temp ^ (temp >> 1)) & 0x40) flags |= V_FLAG; \
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cpu_state.flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) cpu_state.flags |= C_FLAG; \
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if ((temp ^ (temp >> 1)) & 0x40) cpu_state.flags |= V_FLAG; \
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CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
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PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
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break; \
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@ -105,9 +105,9 @@
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c--; \
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} \
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seteaw(temp); if (cpu_state.abrt) return 1; \
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flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) flags |= C_FLAG; \
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if ((flags & C_FLAG) ^ (temp >> 15)) flags |= V_FLAG; \
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cpu_state.flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) cpu_state.flags |= C_FLAG; \
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if ((cpu_state.flags & C_FLAG) ^ (temp >> 15)) cpu_state.flags |= V_FLAG; \
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
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PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
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break; \
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@ -120,14 +120,14 @@
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c--; \
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} \
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seteaw(temp); if (cpu_state.abrt) return 1; \
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flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) flags |= C_FLAG; \
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if ((temp ^ (temp >> 1)) & 0x4000) flags |= V_FLAG; \
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cpu_state.flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) cpu_state.flags |= C_FLAG; \
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if ((temp ^ (temp >> 1)) & 0x4000) cpu_state.flags |= V_FLAG; \
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
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PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
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break; \
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case 0x10: /*RCL w, c*/ \
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temp2 = flags & C_FLAG; \
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temp2 = cpu_state.flags & C_FLAG; \
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if (is486) CLOCK_CYCLES_ALWAYS(c); \
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while (c > 0) \
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{ \
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@ -137,14 +137,14 @@
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c--; \
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} \
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seteaw(temp); if (cpu_state.abrt) return 1; \
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flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) flags |= C_FLAG; \
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if ((flags & C_FLAG) ^ (temp >> 15)) flags |= V_FLAG; \
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cpu_state.flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) cpu_state.flags |= C_FLAG; \
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if ((cpu_state.flags & C_FLAG) ^ (temp >> 15)) cpu_state.flags |= V_FLAG; \
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CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
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PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
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break; \
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case 0x18: /*RCR w, c*/ \
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temp2 = flags & C_FLAG; \
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temp2 = cpu_state.flags & C_FLAG; \
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if (is486) CLOCK_CYCLES_ALWAYS(c); \
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while (c > 0) \
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{ \
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@ -154,9 +154,9 @@
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c--; \
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} \
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seteaw(temp); if (cpu_state.abrt) return 1; \
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flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) flags |= C_FLAG; \
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if ((temp ^ (temp >> 1)) & 0x4000) flags |= V_FLAG; \
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cpu_state.flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) cpu_state.flags |= C_FLAG; \
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if ((temp ^ (temp >> 1)) & 0x4000) cpu_state.flags |= V_FLAG; \
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CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
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PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
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break; \
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@ -197,9 +197,9 @@
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c--; \
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} \
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seteal(temp); if (cpu_state.abrt) return 1; \
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flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) flags |= C_FLAG; \
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if ((flags & C_FLAG) ^ (temp >> 31)) flags |= V_FLAG; \
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cpu_state.flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) cpu_state.flags |= C_FLAG; \
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if ((cpu_state.flags & C_FLAG) ^ (temp >> 31)) cpu_state.flags |= V_FLAG; \
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
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PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
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break; \
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@ -212,9 +212,9 @@
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c--; \
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} \
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seteal(temp); if (cpu_state.abrt) return 1; \
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flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) flags |= C_FLAG; \
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if ((temp ^ (temp >> 1)) & 0x40000000) flags |= V_FLAG; \
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cpu_state.flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) cpu_state.flags |= C_FLAG; \
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if ((temp ^ (temp >> 1)) & 0x40000000) cpu_state.flags |= V_FLAG; \
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CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
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PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
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break; \
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@ -229,14 +229,14 @@
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c--; \
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} \
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seteal(temp); if (cpu_state.abrt) return 1; \
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flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) flags |= C_FLAG; \
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if ((flags & C_FLAG) ^ (temp >> 31)) flags |= V_FLAG; \
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cpu_state.flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) cpu_state.flags |= C_FLAG; \
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if ((cpu_state.flags & C_FLAG) ^ (temp >> 31)) cpu_state.flags |= V_FLAG; \
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CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
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PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
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break; \
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case 0x18: /*RCR l, c*/ \
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temp2 = flags & C_FLAG; \
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temp2 = cpu_state.flags & C_FLAG; \
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if (is486) CLOCK_CYCLES_ALWAYS(c); \
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while (c > 0) \
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{ \
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@ -246,9 +246,9 @@
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c--; \
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} \
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seteal(temp); if (cpu_state.abrt) return 1; \
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flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) flags |= C_FLAG; \
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if ((temp ^ (temp >> 1)) & 0x40000000) flags |= V_FLAG; \
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cpu_state.flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) cpu_state.flags |= C_FLAG; \
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if ((temp ^ (temp >> 1)) & 0x40000000) cpu_state.flags |= V_FLAG; \
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CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
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PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
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break; \
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@ -541,7 +541,7 @@ static int opD3_l_a32(uint32_t fetchdat)
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seteaw(tempw); if (cpu_state.abrt) return 1; \
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setznp16(tempw); \
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flags_rebuild(); \
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if (tempc) flags |= C_FLAG; \
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if (tempc) cpu_state.flags |= C_FLAG; \
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}
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#define SHLD_l() \
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@ -553,7 +553,7 @@ static int opD3_l_a32(uint32_t fetchdat)
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seteal(templ); if (cpu_state.abrt) return 1; \
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setznp32(templ); \
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flags_rebuild(); \
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if (tempc) flags |= C_FLAG; \
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if (tempc) cpu_state.flags |= C_FLAG; \
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}
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@ -567,7 +567,7 @@ static int opD3_l_a32(uint32_t fetchdat)
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seteaw(tempw); if (cpu_state.abrt) return 1; \
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setznp16(tempw); \
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flags_rebuild(); \
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if (tempc) flags |= C_FLAG; \
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if (tempc) cpu_state.flags |= C_FLAG; \
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}
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#define SHRD_l() \
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@ -579,7 +579,7 @@ static int opD3_l_a32(uint32_t fetchdat)
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seteal(templ); if (cpu_state.abrt) return 1; \
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setznp32(templ); \
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flags_rebuild(); \
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if (tempc) flags |= C_FLAG; \
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if (tempc) cpu_state.flags |= C_FLAG; \
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}
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#define opSHxD(operation) \
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