Added Hyundai Super-286TR emulation. Patch from EluanCM.
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SarahW
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12 changed files with 362 additions and 3 deletions
323
src/f82c710_upc.c
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323
src/f82c710_upc.c
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/*
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* Chips & Technologies F82C710 Universal Peripheral Controller (UPC)
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*
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* Copyright (c) 2020 Eluan Costa Miranda <eluancm@gmail.com> All rights reserved.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* =============================================================================
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*
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* This SuperIO chip is commonly seem paired with the Single-chip AT (SCAT)
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* chip. Only the functionality needed for the Hyundai Super-286TR BIOS is
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* implented for now.
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*
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* One of the goals of this chip was getting rid of jumpers and have everything
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* configured by software, but there is no configuration for serial and
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* parallel IRQs. Because of that, motherboards still supply jumpers for these
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* two signals.
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*
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*/
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#include "ibm.h"
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#include "fdc.h"
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#include "ide.h"
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#include "io.h"
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#include "lpt.h"
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#include "serial.h"
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typedef struct upc_t
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{
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int configuration_state; // state of algorithm to enter configuration mode
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int configuration_mode;
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uint16_t cri_addr; // cri = configuration index register, addr is even
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uint16_t cap_addr; // cap = configuration access port, addr is odd and is cri_addr + 1
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uint8_t cri; // currently indexed register
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// these regs are not affected by reset
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uint8_t regs[15]; // there are 16 indexes, but there is no need to store the last one which is: R = cri_addr / 4, W = exit config mode
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int serial_irq;
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int parallel_irq; // TODO: currently not implemented in PCem
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} upc_t;
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static upc_t upc;
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void upc_update_ports(upc_t *upc)
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{
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serial1_remove();
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serial2_remove();
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lpt1_remove();
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lpt2_remove();
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fdc_remove();
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ide_pri_disable();
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ide_sec_disable();
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if (upc->regs[0] & 0x4)
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{
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serial1_init(upc->regs[4] * 4, upc->serial_irq, 0);
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pclog("UPC: UART at %04X, irq %d\n", upc->regs[4] * 4, upc->serial_irq);
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}
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else
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pclog("UPC: UART disabled\n");
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if (upc->regs[0] & 0x8)
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{
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lpt1_init(upc->regs[6] * 4);
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pclog("UPC: PARALLEL at %04X, irq %d\n", upc->regs[6] * 4, upc->parallel_irq);
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}
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else
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pclog("UPC: PARALLEL disabled\n");
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if (upc->regs[12] & 0x80)
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{
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ide_pri_enable();
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pclog("UPC: IDE enabled\n");
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}
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else
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pclog("UPC: IDE disabled\n");
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if (upc->regs[12] & 0x20)
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{
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fdc_add();
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pclog("UPC: FDC enabled\n");
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}
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else
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pclog("UPC: FDC disabled\n");
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if ((upc->regs[0] & 0x60) != 0)
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pclog("UPC: Oscillator control not implemented!\n");
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if ((upc->regs[1] & 0x80) != 0)
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pclog("UPC: Restricted serial reset not implemented!\n");
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if ((upc->regs[1] & 0x80) != 0)
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pclog("UPC: Restricted serial reset not implemented!\n");
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if ((upc->regs[1] & 0x40) != 0)
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pclog("UPC: Bidirectional parallel port support not implemented!\n");
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if ((upc->regs[1] & 0x38) != 0)
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pclog("UPC: UART force CTS, DSR, DCD not implemented!\n");
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if ((upc->regs[2] & 0x70) != 0)
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pclog("UPC: UART clock control not implemented!\n");
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if (upc->regs[9] == 0xb0)
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pclog("UPC: GPCS not implemented! (at default address: %04X)\n", upc->regs[9] * 4);
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else if (upc->regs[9] != 0)
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pclog("UPC: GPCS not implemented! (at address: %04X)\n", upc->regs[9] * 4);
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if ((upc->regs[12] & 0x40) != 0)
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pclog("UPC: IDE XT mode not implemented!\n");
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if ((upc->regs[12] & 0x10) != 0)
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pclog("UPC: FDC power down mode not implemented!\n");
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if ((upc->regs[12] & 0x0C) != 0)
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pclog("UPC: RTCCS not implemented!\n");
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if ((upc->regs[12] & 0x01) != 0)
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pclog("UPC: PS/2 mouse port power down not implemented!\n");
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if (upc->regs[13] != 0)
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pclog("UPC: PS/2 mouse port not implemented!\n");
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if (upc->regs[14] != 0)
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pclog("UPC: Test mode not implemented!\n");
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// regs 10 and 11 not looked at
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}
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uint8_t upc_config_read(uint16_t port, void *priv)
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{
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upc_t *upc = (upc_t *)priv;
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uint8_t temp = 0xff;
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if (upc->configuration_mode)
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{
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if (port == upc->cri_addr)
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{
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temp = upc->cri;
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}
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else if (port == upc->cap_addr)
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{
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if (upc->cri == 0xf)
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temp = upc->cri_addr / 4;
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else
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temp = upc->regs[upc->cri];
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}
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}
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// pclog("UPC READ : %04X, %02X\n", port, temp);
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return temp;
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}
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void upc_config_write(uint16_t port, uint8_t val, void *priv)
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{
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upc_t *upc = (upc_t *)priv;
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int configuration_state_event = 0;
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// pclog("UPC WRITE: %04X, %02X\n", port, val);
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switch(port)
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{
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case 0x2fa:
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if (upc->configuration_state == 0 && val == 0x55)
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configuration_state_event = 1;
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else if (upc->configuration_state == 4)
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{
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uint8_t addr_verify = upc->cri_addr / 4;
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addr_verify += val;
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if (addr_verify == 0xff)
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{
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upc->configuration_mode = 1;
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// TODO: is the value of cri reset here or when exiting configuration mode?
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io_sethandler(upc->cri_addr, 0x0002, upc_config_read, NULL, NULL, upc_config_write, NULL, NULL, upc);
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pclog("UPC: in configuration mode at %04X\n", upc->cri_addr);
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}
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else
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{
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upc->configuration_mode = 0;
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pclog("UPC: configuration mode failed (sum = %02X)\n", addr_verify);
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}
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}
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break;
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case 0x3fa:
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if (upc->configuration_state == 1 && val == 0xaa)
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configuration_state_event = 1;
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else if (upc->configuration_state == 2 && val == 0x36)
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configuration_state_event = 1;
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else if (upc->configuration_state == 3)
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{
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upc->cri_addr = val * 4;
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upc->cap_addr = upc->cri_addr + 1;
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configuration_state_event = 1;
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}
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break;
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default:
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break;
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}
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if (upc->configuration_mode)
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{
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if (port == upc->cri_addr)
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{
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upc->cri = val & 0xf;
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}
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else if (port == upc->cap_addr)
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{
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if (upc->cri == 0xf)
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{
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pclog("UPC: exiting configuration mode\n");
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upc->configuration_mode = 0;
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io_removehandler(upc->cri_addr, 0x0002, upc_config_read, NULL, NULL, upc_config_write, NULL, NULL, upc);
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upc_update_ports(upc); // TODO: any benefit in updating at each register write instead of when exiting config mode?
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}
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else
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{
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upc->regs[upc->cri] = val;
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}
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}
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}
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// TODO: is the state only reset when accessing 0x2fa and 0x3fa wrongly?
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if ((port == 0x2fa || port == 0x3fa) && configuration_state_event)
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upc->configuration_state++;
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else
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upc->configuration_state = 0;
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}
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static void *upc_init()
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{
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pclog("UPC INIT\n");
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memset(&upc, 0, sizeof(upc));
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upc.serial_irq = device_get_config_int("serial_irq");
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upc.parallel_irq = device_get_config_int("parallel_irq");
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// because of these addresses, serial ports must be 16450 without fifos
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io_sethandler(0x02fa, 0x0001, NULL, NULL, NULL, upc_config_write, NULL, NULL, &upc);
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io_sethandler(0x03fa, 0x0001, NULL, NULL, NULL, upc_config_write, NULL, NULL, &upc);
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upc.regs[0] = 0x0c;
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upc.regs[1] = 0x00;
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upc.regs[2] = 0x00;
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upc.regs[3] = 0x00;
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upc.regs[4] = 0xfe;
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upc.regs[5] = 0x00;
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upc.regs[6] = 0x9e;
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upc.regs[7] = 0x00;
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upc.regs[8] = 0x00;
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upc.regs[9] = 0xb0;
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upc.regs[10] = 0x00;
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upc.regs[11] = 0x00;
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upc.regs[12] = 0xa0;
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upc.regs[13] = 0x00;
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upc.regs[14] = 0x00;
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upc_update_ports(&upc);
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return &upc;
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}
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static device_config_t upc_config[] =
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{
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{
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.name = "serial_irq",
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.description = "Serial Port IRQ",
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.type = CONFIG_SELECTION,
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.selection =
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{
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{
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.description = "IRQ 4 (for address 0x3F8/COM1)",
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.value = 4
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},
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{
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.description = "IRQ 3 (for address 0x2F8/COM2)",
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.value = 3
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},
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{
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.description = "Disabled",
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.value = 0 // TODO: see if this breaks PCem's PIC
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}
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},
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.default_int = 4
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},
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{
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.name = "parallel_irq",
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.description = "Parallel Port IRQ",
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.type = CONFIG_SELECTION,
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.selection =
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{
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{
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.description = "IRQ 7 (for address 0x378/LPTB)",
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.value = 7
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},
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{
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.description = "IRQ 5 (for address 0x278/LPTC)",
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.value = 5
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},
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{
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.description = "Disabled",
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.value = 0 // TODO: see if this breaks PCem's PIC
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}
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},
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.default_int = 7
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},
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// For the Hyundai Super-286TR, the only other jumper is the Color/Mono one and it's handled by the at keyboard controller code.
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{
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.type = -1
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}
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};
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device_t f82c710_upc_device =
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{
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"F82C710 UPC",
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0,
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upc_init,
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NULL,
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NULL,
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NULL,
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NULL,
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NULL,
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upc_config
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};
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