Added new SCAT chipset machines - GW-286CT GEAR, Samsung SPC-4216P and KMX-C-02. Patch from Greatpsycho.
This commit is contained in:
SarahW
parent
c532d874a1
commit
9f2b58b7c4
6 changed files with 216 additions and 31 deletions
182
src/scat.c
182
src/scat.c
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@ -19,6 +19,13 @@ static mem_mapping_t scat_shadowram_mapping[6];
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static mem_mapping_t scat_4000_9FFF_mapping[24];
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static mem_mapping_t scat_A000_BFFF_mapping;
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// TODO - 82C836 chipset's memory address mapping isn't fully implemented yet, so memory configuration is hardcoded now.
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static int scatsx_mem_conf_val[33] = { 0x00, 0x01, 0x03, 0x04, 0x05, 0x08, 0x06, 0x06,
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0x0c, 0x09, 0x07, 0x07, 0x0d, 0x0a, 0x0f, 0x0f,
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0x0e, 0x0e, 0x10, 0x10, 0x13, 0x13, 0x11, 0x11,
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0x14, 0x14, 0x12, 0x12, 0x15, 0x15, 0x15, 0x15,
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0x16 };
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uint8_t scat_read(uint16_t port, void *priv);
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void scat_write(uint16_t port, uint8_t val, void *priv);
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@ -53,7 +60,7 @@ void scat_shadow_state_update()
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void scat_set_xms_bound(uint8_t val)
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{
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uint32_t max_xms_size = (mem_size >= 16384) ? 0xFC0000 : mem_size << 10;
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uint32_t max_xms_size = (mem_size >= 16128) ? (((scat_regs[SCAT_VERSION] & 0xF0) != 0 && ((val & 0x10) != 0)) ? 0xFE0000 : 0xFC0000) : mem_size << 10;
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int i;
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switch (val & 0x0F)
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@ -77,26 +84,38 @@ void scat_set_xms_bound(uint8_t val)
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scat_xms_bound = 0x400000;
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break;
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case 7:
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scat_xms_bound = 0x600000;
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scat_xms_bound = (scat_regs[SCAT_VERSION] & 0xF0) == 0 ? 0x600000 : 0x500000;
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break;
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case 8:
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scat_xms_bound = 0x800000;
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scat_xms_bound = (scat_regs[SCAT_VERSION] & 0xF0) == 0 ? 0x800000 : 0x700000;
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break;
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case 9:
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scat_xms_bound = 0xA00000;
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scat_xms_bound = (scat_regs[SCAT_VERSION] & 0xF0) == 0 ? 0xA00000 : 0x800000;
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break;
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case 10:
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scat_xms_bound = 0xC00000;
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scat_xms_bound = (scat_regs[SCAT_VERSION] & 0xF0) == 0 ? 0xC00000 : 0x900000;
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break;
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case 11:
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scat_xms_bound = 0xE00000;
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scat_xms_bound = (scat_regs[SCAT_VERSION] & 0xF0) == 0 ? 0xE00000 : 0xA00000;
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break;
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case 12:
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scat_xms_bound = (scat_regs[SCAT_VERSION] & 0xF0) == 0 ? max_xms_size : 0xB00000;
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break;
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case 13:
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scat_xms_bound = (scat_regs[SCAT_VERSION] & 0xF0) == 0 ? max_xms_size : 0xC00000;
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break;
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case 14:
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scat_xms_bound = (scat_regs[SCAT_VERSION] & 0xF0) == 0 ? max_xms_size : 0xD00000;
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break;
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case 15:
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scat_xms_bound = (scat_regs[SCAT_VERSION] & 0xF0) == 0 ? max_xms_size : 0xF00000;
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break;
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default:
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scat_xms_bound = (mem_size >= 16384 ? 0xFC0000 : mem_size << 10);
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scat_xms_bound = max_xms_size;
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break;
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}
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if ((val & 0x40) == 0 && (scat_regs[SCAT_DRAM_CONFIGURATION] & 0x0F) == 3)
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if ((((scat_regs[SCAT_VERSION] & 0xF0) == 0) && (val & 0x40) == 0 && (scat_regs[SCAT_DRAM_CONFIGURATION] & 0x0F) == 3) || (((scat_regs[SCAT_VERSION] & 0xF0) != 0) && (scat_regs[SCAT_DRAM_CONFIGURATION] & 0x1F) == 3))
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{
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if (val != 1)
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{
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@ -139,17 +158,25 @@ uint32_t get_scat_addr(uint32_t addr, scat_t *p)
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if (p && (scat_regs[SCAT_EMS_CONTROL] & 0x80) && (p->regs_2x9 & 0x80))
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addr = (addr & 0x3fff) | (((p->regs_2x9 & 3) << 8) | p->regs_2x8) << 14;
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if (mem_size < 2048 && ((scat_regs[SCAT_DRAM_CONFIGURATION] & 0x0F) > 7 || (scat_regs[SCAT_EXTENDED_BOUNDARY] & 0x40) != 0))
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addr = (addr & ~0x780000) | ((addr & 0x600000) >> 2);
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else if((scat_regs[SCAT_DRAM_CONFIGURATION] & 0x0F) < 8 && (scat_regs[SCAT_EXTENDED_BOUNDARY] & 0x40) == 0)
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if ((scat_regs[SCAT_VERSION] & 0xF0) == 0)
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{
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addr &= ~0x600000;
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if(mem_size >= 2048)
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addr |= (addr & 0x180000) << 2;
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}
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if (mem_size < 2048 && ((scat_regs[SCAT_DRAM_CONFIGURATION] & 0x0F) > 7 || (scat_regs[SCAT_EXTENDED_BOUNDARY] & 0x40) != 0))
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addr = (addr & ~0x780000) | ((addr & 0x600000) >> 2);
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else if((scat_regs[SCAT_DRAM_CONFIGURATION] & 0x0F) < 8 && (scat_regs[SCAT_EXTENDED_BOUNDARY] & 0x40) == 0)
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{
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addr &= ~0x600000;
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if(mem_size > 2048 || (mem_size == 2048 && (scat_regs[SCAT_DRAM_CONFIGURATION] & 0x0F) < 6))
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addr |= (addr & 0x180000) << 2;
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}
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if ((scat_regs[SCAT_EXTENDED_BOUNDARY] & 0x40) == 0 && (scat_regs[SCAT_DRAM_CONFIGURATION] & 0x0F) == 3 && (addr & ~0x600000) >= 0x100000 && (addr & ~0x600000) < 0x160000)
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addr ^= mem_size < 2048 ? 0x1F0000 : 0x670000;
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if ((scat_regs[SCAT_EXTENDED_BOUNDARY] & 0x40) == 0 && (scat_regs[SCAT_DRAM_CONFIGURATION] & 0x0F) == 3 && (addr & ~0x600000) >= 0x100000 && (addr & ~0x600000) < 0x160000)
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addr ^= mem_size < 2048 ? 0x1F0000 : 0x670000;
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}
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else
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{
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if ((scat_regs[SCAT_DRAM_CONFIGURATION] & 0x1F) == 3 && (addr & ~0x600000) >= 0x100000 && (addr & ~0x600000) < 0x160000)
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addr ^= 0x1F0000;
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}
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return addr;
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}
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@ -179,7 +206,7 @@ void scat_set_global_EMS_state(int state)
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int i;
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uint32_t base_addr, virt_addr;
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for(i=0; i<32; i++)
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for(i=((scat_regs[SCAT_VERSION] & 0xF0) == 0) ? 0 : 24; i<32; i++)
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{
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base_addr = (i + 16) << 14;
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if(i >= 24)
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@ -244,13 +271,13 @@ void scat_write(uint16_t port, uint8_t val, void *priv)
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break;
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case SCAT_POWER_MANAGEMENT:
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// TODO - Only use AUX parity disable bit for this version. Other bits should be implemented later.
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val &= 0x40;
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val &= (scat_regs[SCAT_VERSION] & 0xF0) == 0 ? 0x40 : 0x60;
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scat_reg_valid = 1;
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break;
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case SCAT_DRAM_CONFIGURATION:
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if((scat_regs[SCAT_EXTENDED_BOUNDARY] & 0x40) == 0)
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if((((scat_regs[SCAT_VERSION] & 0xF0) == 0) && (scat_regs[SCAT_EXTENDED_BOUNDARY] & 0x40) == 0) || ((scat_regs[SCAT_VERSION] & 0xF0) != 0))
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{
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if((val & 0x0F) == 3)
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if((((scat_regs[SCAT_VERSION] & 0xF0) == 0) && (val & 0x0F) == 3) || (((scat_regs[SCAT_VERSION] & 0xF0) != 0) && (val & 0x1F) == 3))
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{
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if(mem_size > 1024) mem_mapping_disable(&ram_high_mapping);
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for(index=0;index<6;index++)
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@ -271,13 +298,21 @@ void scat_write(uint16_t port, uint8_t val, void *priv)
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}
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scat_map_update = 1;
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cpu_waitstates = (val & 0x70) == 0 ? 1 : 2;
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cpu_update_waitstates();
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if((scat_regs[SCAT_VERSION] & 0xF0) == 0)
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{
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cpu_waitstates = (val & 0x70) == 0 ? 1 : 2;
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cpu_update_waitstates();
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}
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else
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{
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if(mem_size != 1024 || ((val & 0x1F) != 2 && (val & 0x1F) != 3))
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val = (val & 0xe0) | scatsx_mem_conf_val[mem_size >> 9];
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}
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scat_reg_valid = 1;
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break;
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case SCAT_EXTENDED_BOUNDARY:
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scat_set_xms_bound(val & 0x4f);
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scat_set_xms_bound(val & ((scat_regs[SCAT_VERSION] & 0xF0) == 0 ? 0x4f : 0x1f));
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mem_set_mem_state(0x40000, 0x60000, (val & 0x20) ? MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL : MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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if((val ^ scat_regs[SCAT_EXTENDED_BOUNDARY]) & 0x40) scat_map_update = 1;
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scat_reg_valid = 1;
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@ -290,6 +325,19 @@ void scat_write(uint16_t port, uint8_t val, void *priv)
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scat_reg_valid = 1;
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scat_shadow_update = 1;
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break;
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case SCATSX_LAPTOP_FEATURES:
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if((scat_regs[SCAT_VERSION] & 0xF0) != 0)
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{
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val = (val & ~8) | (scat_regs[SCATSX_LAPTOP_FEATURES] & 8);
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scat_reg_valid = 1;
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}
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break;
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case SCATSX_FAST_VIDEO_CONTROL:
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case SCATSX_FAST_VIDEORAM_ENABLE:
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case SCATSX_HIGH_PERFORMANCE_REFRESH:
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case SCATSX_CAS_TIMING_FOR_DMA:
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if((scat_regs[SCAT_VERSION] & 0xF0) == 0) scat_reg_valid = 1;
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break;
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default:
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break;
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}
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@ -322,7 +370,8 @@ void scat_write(uint16_t port, uint8_t val, void *priv)
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if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == (0x40 | ((port & 0x10) >> 4)))
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{
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// pclog("Write SCAT EMS Control Port %04X to %02X at %04X:%04X\n", port, val, CS, cpu_state.pc);
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index = scat_ems_reg_2xA & 0x1F;
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if((scat_regs[SCAT_VERSION] & 0xF0) == 0) index = scat_ems_reg_2xA & 0x1F;
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else index = ((scat_ems_reg_2xA & 0x40) >> 4) + (scat_ems_reg_2xA & 0x3) + 24;
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scat_stat[index].regs_2x8 = val;
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base_addr = (index + 16) << 14;
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if(index >= 24)
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@ -342,7 +391,8 @@ void scat_write(uint16_t port, uint8_t val, void *priv)
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if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == (0x40 | ((port & 0x10) >> 4)))
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{
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// pclog("Write SCAT EMS Control Port %04X to %02X at %04X:%04X\n", port, val, CS, cpu_state.pc);
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index = scat_ems_reg_2xA & 0x1F;
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if((scat_regs[SCAT_VERSION] & 0xF0) == 0) index = scat_ems_reg_2xA & 0x1F;
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else index = ((scat_ems_reg_2xA & 0x40) >> 4) + (scat_ems_reg_2xA & 0x3) + 24;
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scat_stat[index].regs_2x9 = val;
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base_addr = (index + 16) << 14;
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if(index >= 24)
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@ -371,7 +421,7 @@ void scat_write(uint16_t port, uint8_t val, void *priv)
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if (scat_ems_reg_2xA & 0x80)
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{
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scat_ems_reg_2xA = (scat_ems_reg_2xA & 0xe0) | ((scat_ems_reg_2xA + 1) & 0x1f);
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scat_ems_reg_2xA = (scat_ems_reg_2xA & 0xe0) | ((scat_ems_reg_2xA + 1) & (((scat_regs[SCAT_VERSION] & 0xF0) == 0) ? 0x1f : 3));
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}
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}
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break;
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@ -380,7 +430,7 @@ void scat_write(uint16_t port, uint8_t val, void *priv)
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if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == (0x40 | ((port & 0x10) >> 4)))
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{
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// pclog("Write SCAT EMS Control Port %04X to %02X at %04X:%04X\n", port, val, CS, cpu_state.pc);
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scat_ems_reg_2xA = val;
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scat_ems_reg_2xA = ((scat_regs[SCAT_VERSION] & 0xF0) == 0) ? val : val & 0xc3;
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}
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break;
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}
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@ -398,7 +448,9 @@ uint8_t scat_read(uint16_t port, void *priv)
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val = (scat_regs[scat_index] & 0x3f) | (~nmi_mask & 0x80) | ((mem_a20_key & 2) << 5);
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break;
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case SCAT_DRAM_CONFIGURATION:
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val = (scat_regs[scat_index] & 0x8f) | (cpu_waitstates == 1 ? 0 : 0x10);
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if ((scat_regs[SCAT_VERSION] & 0xF0) == 0) val = (scat_regs[scat_index] & 0x8f) | (cpu_waitstates == 1 ? 0 : 0x10);
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else if(mem_size != 1024) val = (scat_regs[scat_index] & 0xe0) | scatsx_mem_conf_val[mem_size >> 9];
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else val = scat_regs[scat_index];
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break;
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default:
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val = scat_regs[scat_index];
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@ -416,7 +468,8 @@ uint8_t scat_read(uint16_t port, void *priv)
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if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == (0x40 | ((port & 0x10) >> 4)))
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{
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// pclog("Read SCAT EMS Control Port %04X at %04X:%04X\n", port, CS, cpu_state.pc);
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index = scat_ems_reg_2xA & 0x1F;
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if((scat_regs[SCAT_VERSION] & 0xF0) == 0) index = scat_ems_reg_2xA & 0x1F;
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else index = ((scat_ems_reg_2xA & 0x40) >> 4) + (scat_ems_reg_2xA & 0x3) + 24;
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val = scat_stat[index].regs_2x8;
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}
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break;
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@ -425,7 +478,8 @@ uint8_t scat_read(uint16_t port, void *priv)
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if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == (0x40 | ((port & 0x10) >> 4)))
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{
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// pclog("Read SCAT EMS Control Port %04X at %04X:%04X\n", port, CS, cpu_state.pc);
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index = scat_ems_reg_2xA & 0x1F;
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if((scat_regs[SCAT_VERSION] & 0xF0) == 0) index = scat_ems_reg_2xA & 0x1F;
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else index = ((scat_ems_reg_2xA & 0x40) >> 4) + (scat_ems_reg_2xA & 0x3) + 24;
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val = scat_stat[index].regs_2x9;
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}
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break;
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@ -523,3 +577,69 @@ void scat_init()
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scat_set_xms_bound(0);
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scat_shadow_state_update();
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}
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void scatsx_init()
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{
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int i;
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io_sethandler(0x0022, 0x0002, scat_read, NULL, NULL, scat_write, NULL, NULL, NULL);
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io_sethandler(0x0080, 0x0001, scat_read, NULL, NULL, scat_write, NULL, NULL, NULL);
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io_sethandler(0x0092, 0x0001, scat_read, NULL, NULL, scat_write, NULL, NULL, NULL);
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for (i = 0; i < 256; i++)
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{
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scat_regs[i] = 0xff;
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}
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scat_regs[SCAT_DMA_WAIT_STATE_CONTROL] = 0;
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scat_regs[SCAT_VERSION] = 0x13;
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scat_regs[SCAT_CLOCK_CONTROL] = 6;
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scat_regs[SCAT_PERIPHERAL_CONTROL] = 0;
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scat_regs[SCAT_MISCELLANEOUS_STATUS] = 0x37;
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scat_regs[SCAT_POWER_MANAGEMENT] = 0;
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scat_regs[SCAT_ROM_ENABLE] = 0xC0;
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scat_regs[SCAT_RAM_WRITE_PROTECT] = 0;
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scat_regs[SCAT_SHADOW_RAM_ENABLE_1] = 0;
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scat_regs[SCAT_SHADOW_RAM_ENABLE_2] = 0;
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scat_regs[SCAT_SHADOW_RAM_ENABLE_3] = 0;
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scat_regs[SCAT_DRAM_CONFIGURATION] = 1;
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scat_regs[SCAT_EXTENDED_BOUNDARY] = 0;
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scat_regs[SCAT_EMS_CONTROL] = 0;
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scat_regs[SCATSX_LAPTOP_FEATURES] = 0;
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scat_regs[SCATSX_FAST_VIDEO_CONTROL] = 0;
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scat_regs[SCATSX_FAST_VIDEORAM_ENABLE] = 0;
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scat_regs[SCATSX_HIGH_PERFORMANCE_REFRESH] = 8;
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scat_regs[SCATSX_CAS_TIMING_FOR_DMA] = 3;
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scat_port_92 = 0;
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mem_mapping_set_addr(&ram_low_mapping, 0, 0x80000);
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for (i = 16; i < 24; i++)
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{
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mem_mapping_add(&scat_4000_9FFF_mapping[i], 0x40000 + (i << 14), 0x4000, mem_read_scatems, NULL, NULL, mem_write_scatems, NULL, NULL, mem_size > 256 + (i << 4) ? ram + 0x40000 + (i << 14) : NULL, MEM_MAPPING_INTERNAL, NULL);
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mem_mapping_enable(&scat_4000_9FFF_mapping[i]);
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}
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mem_mapping_add(&scat_A000_BFFF_mapping, 0xA0000, 0x20000, mem_read_scatems, NULL, NULL, mem_write_scatems, NULL, NULL, ram + 0xA0000, MEM_MAPPING_INTERNAL, NULL);
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mem_mapping_enable(&scat_A000_BFFF_mapping);
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for (i = 24; i < 32; i++)
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{
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scat_stat[i].regs_2x8 = 0xff;
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scat_stat[i].regs_2x9 = 0x03;
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mem_mapping_add(&scat_mapping[i], (i + 28) << 14, 0x04000, mem_read_scatems, NULL, NULL, mem_write_scatems, NULL, NULL, ram + ((i + 28) << 14), 0, &scat_stat[i]);
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mem_mapping_disable(&scat_mapping[i]);
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}
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// TODO - Only normal CPU accessing address FF0000 to FFFFFF mapped to ROM. Normal CPU accessing address FC0000 to FEFFFF map to ROM should be implemented later.
|
||||
for (i = 12; i < 16; i++)
|
||||
{
|
||||
mem_mapping_add(&scat_high_mapping[i], (i << 14) + 0xFC0000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (i << 14), 0, NULL);
|
||||
}
|
||||
|
||||
for(i=0;i<6;i++)
|
||||
mem_mapping_add(&scat_shadowram_mapping[i], 0x100000 + (i << 16), 0x10000, mem_read_scatems, NULL, NULL, mem_write_scatems, NULL, NULL, mem_size >= 1024 ? ram + get_scat_addr(0x100000 + (i << 16), NULL) : NULL, MEM_MAPPING_INTERNAL, NULL);
|
||||
|
||||
scat_set_xms_bound(0);
|
||||
scat_shadow_state_update();
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue