Implemented effective address compilation.
This commit is contained in:
SarahW
parent
ee3f9210dc
commit
94fea237b4
13 changed files with 978 additions and 133 deletions
245
src/codegen.c
245
src/codegen.c
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@ -9,6 +9,8 @@
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#include "codegen_backend.h"
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#include "codegen_ir.h"
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int has_ea;
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codeblock_t *codeblock;
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codeblock_t **codeblock_hash;
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@ -38,8 +40,211 @@ void codegen_generate_reset()
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last_op_ssegs = -1;
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last_op_ea_seg = NULL;
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last_op_32 = -1;
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has_ea = 0;
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}
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static x86seg *codegen_generate_ea_16_long(ir_data_t *ir, x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, uint32_t *op_pc)
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{
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// pclog("codegen - mod=%i rm=%i reg=%i fetchdat=%08x\n", cpu_mod, cpu_rm, cpu_reg, fetchdat);
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if (!cpu_mod && cpu_rm == 6)
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{
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uint16_t addr = (fetchdat >> 8) & 0xffff;
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uop_MOV_IMM(ir, IREG_eaaddr, addr);
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(*op_pc) += 2;
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}
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else
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{
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int base_reg, index_reg, offset;
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switch (cpu_rm)
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{
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case 0: case 1: case 7:
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base_reg = IREG_EBX;
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break;
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case 2: case 3: case 6:
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base_reg = IREG_EBP;
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break;
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case 4:
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base_reg = IREG_ESI;
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break;
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case 5:
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base_reg = IREG_EDI;
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break;
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}
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uop_MOV(ir, IREG_eaaddr, base_reg);
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if (!(cpu_rm & 4))
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{
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if (!(cpu_rm & 1))
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index_reg = IREG_ESI;
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else
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index_reg = IREG_EDI;
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uop_ADD(ir, IREG_eaaddr, IREG_eaaddr, index_reg);
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}
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switch (cpu_mod)
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{
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case 1:
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offset = (int)(int8_t)((fetchdat >> 8) & 0xff);
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uop_ADD_IMM(ir, IREG_eaaddr, IREG_eaaddr, offset);
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(*op_pc)++;
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break;
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case 2:
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offset = (fetchdat >> 8) & 0xffff;
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uop_ADD_IMM(ir, IREG_eaaddr, IREG_eaaddr, offset);
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(*op_pc) += 2;
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break;
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}
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uop_AND_IMM(ir, IREG_eaaddr, IREG_eaaddr, 0xffff);
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if (mod1seg[cpu_rm] == &ss && !op_ssegs)
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{
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op_ea_seg = &_ss;
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}
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}
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return op_ea_seg;
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}
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static x86seg *codegen_generate_ea_32_long(ir_data_t *ir, x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, uint32_t *op_pc)
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{
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uint32_t new_eaaddr;
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if (cpu_rm == 4)
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{
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uint8_t sib = fetchdat >> 8;
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(*op_pc)++;
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switch (cpu_mod)
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{
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case 0:
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if ((sib & 7) == 5)
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{
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new_eaaddr = fastreadl(cs + (*op_pc) + 1);
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uop_MOV_IMM(ir, IREG_eaaddr, new_eaaddr);
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(*op_pc) += 4;
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}
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else
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{
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uop_MOV(ir, IREG_eaaddr, sib & 7);
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}
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break;
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case 1:
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new_eaaddr = (uint32_t)(int8_t)((fetchdat >> 16) & 0xff);
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uop_MOV_IMM(ir, IREG_eaaddr, new_eaaddr);
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uop_ADD(ir, IREG_eaaddr, IREG_eaaddr, sib & 7);
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(*op_pc)++;
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break;
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case 2:
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new_eaaddr = fastreadl(cs + (*op_pc) + 1);
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uop_MOV_IMM(ir, IREG_eaaddr, new_eaaddr);
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uop_ADD(ir, IREG_eaaddr, IREG_eaaddr, sib & 7);
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(*op_pc) += 4;
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break;
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}
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// if (stack_offset && (sib & 7) == 4 && (cpu_mod || (sib & 7) != 5)) /*ESP*/
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// {
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// addbyte(0x05);
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// addlong(stack_offset);
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// }
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if (((sib & 7) == 4 || (cpu_mod && (sib & 7) == 5)) && !op_ssegs)
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op_ea_seg = &_ss;
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if (((sib >> 3) & 7) != 4)
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{
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switch (sib >> 6)
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{
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case 0:
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uop_ADD(ir, IREG_eaaddr, IREG_eaaddr, (sib >> 3) & 7);
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break;
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case 1:
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uop_ADD_LSHIFT(ir, IREG_eaaddr, IREG_eaaddr, (sib >> 3) & 7, 1);
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break;
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case 2:
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uop_ADD_LSHIFT(ir, IREG_eaaddr, IREG_eaaddr, (sib >> 3) & 7, 2);
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break;
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case 3:
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uop_ADD_LSHIFT(ir, IREG_eaaddr, IREG_eaaddr, (sib >> 3) & 7, 3);
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break;
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}
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}
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}
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else
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{
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if (!cpu_mod && cpu_rm == 5)
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{
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new_eaaddr = fastreadl(cs + (*op_pc) + 1);
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uop_MOV_IMM(ir, IREG_eaaddr, new_eaaddr);
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(*op_pc) += 4;
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return op_ea_seg;
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}
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uop_MOV(ir, IREG_eaaddr, cpu_rm);
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if (cpu_mod)
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{
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if (cpu_rm == 5 && !op_ssegs)
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op_ea_seg = &_ss;
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if (cpu_mod == 1)
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{
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uop_ADD_IMM(ir, IREG_eaaddr, IREG_eaaddr, (uint32_t)(int8_t)(fetchdat >> 8));
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(*op_pc)++;
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}
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else
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{
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new_eaaddr = fastreadl(cs + (*op_pc) + 1);
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uop_ADD_IMM(ir, IREG_eaaddr, IREG_eaaddr, new_eaaddr);
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(*op_pc) += 4;
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}
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}
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}
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return op_ea_seg;
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}
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static uint8_t opcode_modrm[256] =
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{
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1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, /*00*/
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1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, /*10*/
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1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, /*20*/
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1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, /*30*/
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*40*/
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*50*/
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0, 0, 1, 1, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, /*60*/
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*70*/
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /*80*/
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*90*/
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*a0*/
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*b0*/
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1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, /*c0*/
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1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, /*d0*/
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*e0*/
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0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, /*f0*/
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};
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static uint8_t opcode_0f_modrm[256] =
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{
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1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*00*/
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*10*/
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1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*20*/
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*30*/
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /*40*/
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*50*/
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, /*60*/
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0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, /*70*/
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*80*/
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /*90*/
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0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, /*a0*/
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1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, /*b0*/
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1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, /*c0*/
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0, 1, 1, 1, 0, 1, 0, 0, 1, 1, 0, 1, 1, 1, 0, 1, /*d0*/
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0, 1, 1, 0, 0, 1, 0, 0, 1, 1, 0, 1, 1, 1, 0, 1, /*e0*/
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0, 1, 1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 1, 0 /*f0*/
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};
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void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t new_pc, uint32_t old_pc)
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{
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codeblock_t *block = &codeblock[block_current];
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@ -52,6 +257,7 @@ void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t
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x86seg *op_ea_seg = &_ds;
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int op_ssegs = 0;
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int over = 0;
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int test_modrm = 1;
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op_ea_seg = &_ds;
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@ -127,14 +333,44 @@ generate_call:
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//pclog("%04x:%08x : %02x\n", CS, new_pc, opcode);
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op = op_table[((opcode >> opcode_shift) | op_32) & opcode_mask];
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if (!test_modrm ||
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(op_table == x86_dynarec_opcodes && opcode_modrm[opcode]) ||
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(op_table == x86_dynarec_opcodes_0f && opcode_0f_modrm[opcode]))
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{
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//int stack_offset = 0;
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// if (op_table == x86_dynarec_opcodes && opcode == 0x8f) /*POP*/
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// stack_offset = (op_32 & 0x100) ? 4 : 2;
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cpu_mod = (fetchdat >> 6) & 3;
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cpu_reg = (fetchdat >> 3) & 7;
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cpu_rm = fetchdat & 7;
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uop_MOV_IMM(ir, IREG_rm_mod_reg, cpu_rm | (cpu_mod << 8) | (cpu_reg << 16));
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// op_pc += pc_off;
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if (cpu_mod != 3 && !(op_32 & 0x200))
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{
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op_ea_seg = codegen_generate_ea_16_long(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc);
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// has_ea = 1;
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}
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if (cpu_mod != 3 && (op_32 & 0x200))
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{
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op_ea_seg = codegen_generate_ea_32_long(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc);
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// has_ea = 1;
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}
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// op_ea_seg = codegen_generate_ea_32_long(op_ea_seg, fetchdat, op_ssegs, &op_pc, stack_offset);
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// op_pc -= pc_off;
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}
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uop_MOV_IMM(ir, IREG_pc, op_pc);
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uop_MOV_IMM(ir, IREG_oldpc, old_pc);
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if (op_32 != last_op_32)
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uop_MOV_IMM(ir, IREG_op32, op_32);
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/*Lazy ea_seg/ssegs updating isn't safe until EA calculation is implemented*/
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// if (op_ea_seg != last_op_ea_seg)
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if (op_ea_seg != last_op_ea_seg)
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uop_MOV_PTR(ir, IREG_ea_seg, (void *)op_ea_seg);
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// if (op_ssegs != last_op_ssegs)
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if (op_ssegs != last_op_ssegs)
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uop_MOV_IMM(ir, IREG_ssegs, op_ssegs);
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uop_LOAD_FUNC_ARG_IMM(ir, 0, fetchdat);
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uop_CALL_INSTRUCTION_FUNC(ir, op);
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@ -150,4 +386,7 @@ generate_call:
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CPU_BLOCK_END();
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codegen_endpc = (cs + cpu_state.pc) + 8;
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// if (has_ea)
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// fatal("Has EA\n");
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}
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