Now up to date with current dev version.
Changes since v0.7 : - Major CPU reorganisation. This has possibly broken some stuff, though I fixed all the regressions I could find - Lazy flags. This brought 10% speed improvement at one point, but that's probably been lost now - 430 VX chipset emulation - IDT Winchip emulation (currently sans MMX). Timing is probably wrong - Fixed a few FPU bugs - Timer reorganisation - Sound reorganisation - Other general reorganisation - AdLib Gold emulation - Windows Sound System emulation - Pro Audio Spectrum 16 emulation. This currently works with most DOS stuff, but not in Windows - Major improvements to GUS emulation. Has the downside that it now conflicts with SB emulation, so probably best to not enable both simultaneously - New graphics cards : - ATI-18800 (VGA Edge-16) - ATI-28800 (VGA Charger) - ATI Mach64GX (Graphics Pro Turbo). Quite a few features missing, but Windows doesn't seem to use half the features of this card - Cirrus Logic CL-GD5429. Blitter is a bit broken - Oak OTI-067 - S3 Trio64 (Number Nine 9FX) - S3 Virge. Only framebuffer stuff at the minute, Windows won't recognise the card - Trident TGUI-9440 - VGA. Doesn't work yet - Beginnings of 3DFX emulation, however this is in extremely early stages and doesn't do anything useful - Fixed DMA bug stopping floppy drives working in Windows 3.x - Fixed some other stuff probably - Broke some other stuff probably as well
This commit is contained in:
TomW
parent
3c253c2cf8
commit
9312de19ac
87 changed files with 4528 additions and 9373 deletions
149
src/vid_s3.c
149
src/vid_s3.c
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@ -1,17 +1,19 @@
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/*S3 emulation*/
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#include "ibm.h"
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#include "io.h"
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#include "mem.h"
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#include "pci.h"
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#include "video.h"
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#include "vid_svga.h"
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#include "vid_svga_render.h"
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#include "vid_sdac_ramdac.h"
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void s3_updatemapping();
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void s3_accel_write(uint32_t addr, uint8_t val);
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void s3_accel_write_w(uint32_t addr, uint16_t val);
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void s3_accel_write_l(uint32_t addr, uint32_t val);
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uint8_t s3_accel_read(uint32_t addr);
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void s3_accel_write(uint32_t addr, uint8_t val, void *priv);
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void s3_accel_write_w(uint32_t addr, uint16_t val, void *priv);
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void s3_accel_write_l(uint32_t addr, uint32_t val, void *priv);
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uint8_t s3_accel_read(uint32_t addr, void *priv);
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static uint8_t s3_bank;
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static uint8_t s3_ma_ext;
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@ -20,7 +22,7 @@ static int s3_bpp = 0;
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static uint8_t s3_id, s3_id_ext;
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void s3_out(uint16_t addr, uint8_t val)
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void s3_out(uint16_t addr, uint8_t val, void *priv)
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{
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uint8_t old;
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@ -40,7 +42,7 @@ void s3_out(uint16_t addr, uint8_t val)
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case 0x3C6: case 0x3C7: case 0x3C8: case 0x3C9:
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// pclog("Write RAMDAC %04X %02X %04X:%04X\n", addr, val, CS, pc);
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sdac_ramdac_out(addr,val);
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sdac_ramdac_out(addr, val, NULL);
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return;
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case 0x3D4:
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@ -141,13 +143,11 @@ void s3_out(uint16_t addr, uint8_t val)
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}
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break;
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}
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svga_out(addr,val);
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svga_out(addr, val, NULL);
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}
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uint8_t s3_in(uint16_t addr)
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uint8_t s3_in(uint16_t addr, void *priv)
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{
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uint8_t temp;
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if (((addr&0xFFF0) == 0x3D0 || (addr&0xFFF0) == 0x3B0) && !(svga_miscout&1)) addr ^= 0x60;
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// if (addr != 0x3da) pclog("S3 in %04X\n", addr);
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@ -155,7 +155,7 @@ uint8_t s3_in(uint16_t addr)
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{
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case 0x3C6: case 0x3C7: case 0x3C8: case 0x3C9:
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// pclog("Read RAMDAC %04X %04X:%04X\n", addr, CS, pc);
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return sdac_ramdac_in(addr);
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return sdac_ramdac_in(addr, NULL);
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case 0x3D4:
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return crtcreg;
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@ -174,7 +174,7 @@ uint8_t s3_in(uint16_t addr)
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}
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return crtc[crtcreg];
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}
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return svga_in(addr);
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return svga_in(addr, NULL);
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}
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void s3_recalctimings()
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@ -182,7 +182,27 @@ void s3_recalctimings()
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// pclog("recalctimings\n");
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svga_ma |= (s3_ma_ext << 16);
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// pclog("SVGA_MA %08X\n", svga_ma);
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if (gdcreg[5] & 0x40) svga_lowres = !(crtc[0x3a] & 0x10);
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if ((gdcreg[5] & 0x40) && (crtc[0x3a] & 0x10))
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{
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switch (bpp)
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{
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case 8:
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svga_render = svga_render_8bpp_highres;
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break;
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case 15:
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svga_render = svga_render_15bpp_highres;
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break;
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case 16:
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svga_render = svga_render_16bpp_highres;
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break;
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case 24:
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svga_render = svga_render_24bpp_highres;
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break;
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case 32:
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svga_render = svga_render_32bpp_highres;
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break;
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}
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}
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if (crtc[0x5d] & 0x01) svga_htotal += 0x100;
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if (crtc[0x5d] & 0x02) svga_hdisp += 0x100;
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if (crtc[0x5e] & 0x01) svga_vtotal += 0x400;
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@ -201,25 +221,25 @@ void s3_recalctimings()
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static uint32_t s3_linear_base = 0, s3_linear_size = 0;
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void s3_updatemapping()
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{
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mem_removehandler(s3_linear_base, s3_linear_size, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear);
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mem_removehandler(s3_linear_base, s3_linear_size, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, NULL);
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// video_write_a000_w = video_write_a000_l = NULL;
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mem_removehandler(0xa0000, 0x20000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel);
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mem_removehandler(0xa0000, 0x20000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, NULL);
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// pclog("Update mapping - bank %02X ", gdcreg[6] & 0xc);
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switch (gdcreg[6] & 0xc) /*Banked framebuffer*/
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{
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case 0x0: /*128k at A0000*/
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mem_sethandler(0xa0000, 0x20000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel);
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mem_sethandler(0xa0000, 0x20000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, NULL);
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break;
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case 0x4: /*64k at A0000*/
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mem_sethandler(0xa0000, 0x10000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel);
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mem_sethandler(0xa0000, 0x10000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, NULL);
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break;
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case 0x8: /*32k at B0000*/
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mem_sethandler(0xb0000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel);
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mem_sethandler(0xb0000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, NULL);
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break;
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case 0xC: /*32k at B8000*/
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mem_sethandler(0xb8000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel);
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mem_sethandler(0xb8000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, NULL);
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break;
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}
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@ -246,15 +266,15 @@ void s3_updatemapping()
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// pclog("%08X %08X %02X %02X %02X\n", linear_base, linear_size, crtc[0x58], crtc[0x59], crtc[0x5a]);
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// pclog("Linear framebuffer at %08X size %08X\n", linear_base, linear_size);
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if (s3_linear_base == 0xa0000)
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mem_sethandler(0xa0000, 0x10000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel);
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mem_sethandler(0xa0000, 0x10000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, NULL);
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else
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mem_sethandler(s3_linear_base, s3_linear_size, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear);
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mem_sethandler(s3_linear_base, s3_linear_size, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, NULL);
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}
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// pclog("Memory mapped IO %02X\n", crtc[0x53] & 0x10);
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if (crtc[0x53] & 0x10) /*Memory mapped IO*/
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{
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mem_sethandler(0xa0000, 0x10000, s3_accel_read, NULL, NULL, s3_accel_write, s3_accel_write_w, s3_accel_write_l);
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mem_sethandler(0xa0000, 0x10000, s3_accel_read, NULL, NULL, s3_accel_write, s3_accel_write_w, s3_accel_write_l, NULL);
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/* video_write_a000 = s3_accel_write;
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video_write_a000_w = s3_accel_write_w;
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video_write_a000_l = s3_accel_write_l;
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@ -299,7 +319,7 @@ struct
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void s3_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat);
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void s3_accel_out(uint16_t port, uint8_t val)
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void s3_accel_out(uint16_t port, uint8_t val, void *priv)
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{
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// pclog("Accel out %04X %02X\n", port, val);
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switch (port)
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@ -503,7 +523,7 @@ void s3_accel_out(uint16_t port, uint8_t val)
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}
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}
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void s3_accel_out_w(uint16_t port, uint16_t val)
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void s3_accel_out_w(uint16_t port, uint16_t val, void *priv)
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{
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// pclog("Accel out w %04X %04X\n", port, val);
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if (s3_accel.cmd & 0x100)
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@ -519,7 +539,7 @@ void s3_accel_out_w(uint16_t port, uint16_t val)
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}
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}
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void s3_accel_out_l(uint16_t port, uint32_t val)
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void s3_accel_out_l(uint16_t port, uint32_t val, void *priv)
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{
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// pclog("Accel out l %04X %08X\n", port, val);
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if (s3_accel.cmd & 0x100)
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@ -563,7 +583,7 @@ void s3_accel_out_l(uint16_t port, uint32_t val)
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}
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}
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uint8_t s3_accel_in(uint16_t port)
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uint8_t s3_accel_in(uint16_t port, void *priv)
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{
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int temp;
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// pclog("Accel in %04X\n", port);
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@ -682,11 +702,11 @@ uint8_t s3_accel_in(uint16_t port)
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return 0;
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}
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void s3_accel_write(uint32_t addr, uint8_t val)
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void s3_accel_write(uint32_t addr, uint8_t val, void *priv)
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{
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// pclog("Write S3 accel %08X %02X\n", addr, val);
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if (addr & 0x8000)
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s3_accel_out(addr & 0xffff, val);
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s3_accel_out(addr & 0xffff, val, priv);
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else
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{
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if (s3_accel.cmd & 0x100)
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@ -699,13 +719,13 @@ void s3_accel_write(uint32_t addr, uint8_t val)
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}
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}
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void s3_accel_write_w(uint32_t addr, uint16_t val)
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void s3_accel_write_w(uint32_t addr, uint16_t val, void *priv)
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{
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// pclog("Write S3 accel w %08X %04X\n", addr, val);
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if (addr & 0x8000)
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{
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s3_accel_out( addr & 0xffff, val);
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s3_accel_out((addr & 0xffff) + 1, val >> 8);
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s3_accel_out( addr & 0xffff, val, priv);
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s3_accel_out((addr & 0xffff) + 1, val >> 8, priv);
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}
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else
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{
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@ -723,15 +743,15 @@ void s3_accel_write_w(uint32_t addr, uint16_t val)
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}
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}
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void s3_accel_write_l(uint32_t addr, uint32_t val)
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void s3_accel_write_l(uint32_t addr, uint32_t val, void *priv)
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{
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// pclog("Write S3 accel l %08X %08X\n", addr, val);
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if (addr & 0x8000)
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{
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s3_accel_out( addr & 0xffff, val);
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s3_accel_out((addr & 0xffff) + 1, val >> 8);
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s3_accel_out((addr & 0xffff) + 2, val >> 16);
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s3_accel_out((addr & 0xffff) + 3, val >> 24);
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s3_accel_out( addr & 0xffff, val, priv);
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s3_accel_out((addr & 0xffff) + 1, val >> 8, priv);
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s3_accel_out((addr & 0xffff) + 2, val >> 16, priv);
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s3_accel_out((addr & 0xffff) + 3, val >> 24, priv);
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}
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else
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{
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@ -777,11 +797,11 @@ void s3_accel_write_l(uint32_t addr, uint32_t val)
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}
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}
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uint8_t s3_accel_read(uint32_t addr)
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uint8_t s3_accel_read(uint32_t addr, void *priv)
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{
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// pclog("Read S3 accel %08X\n", addr);
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if (addr & 0x8000)
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return s3_accel_in(addr & 0xffff);
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return s3_accel_in(addr & 0xffff, priv);
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return 0;
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}
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@ -828,12 +848,8 @@ uint8_t s3_accel_read(uint32_t addr)
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void s3_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat)
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{
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uint32_t dest, destbak;
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int sx, sy, cx, cy;
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int x, y;
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uint32_t src_dat, dest_dat;
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int frgd_mix, bkgd_mix;
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int mix;
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int clip_t = s3_accel.multifunc[1] & 0xfff;
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int clip_l = s3_accel.multifunc[2] & 0xfff;
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int clip_b = s3_accel.multifunc[3] & 0xfff;
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@ -1390,6 +1406,7 @@ void s3_hwcursor_draw(int displine)
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int xx;
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int offset = svga_hwcursor_latch.x - svga_hwcursor_latch.xoff;
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pclog("HWcursor %i %i\n", svga_hwcursor_latch.x, svga_hwcursor_latch.y);
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for (x = 0; x < 64; x += 16)
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{
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dat[0] = (vram[svga_hwcursor_latch.addr] << 8) | vram[svga_hwcursor_latch.addr + 1];
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@ -1414,9 +1431,9 @@ void s3_hwcursor_draw(int displine)
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}
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uint8_t s3_pci_read(int func, int addr)
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uint8_t s3_pci_read(int func, int addr, void *priv)
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{
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pclog("S3 PCI read %08X\n", addr);
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// pclog("S3 PCI read %08X\n", addr);
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switch (addr)
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{
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case 0x00: return 0x33; /*'S3'*/
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@ -1448,7 +1465,7 @@ uint8_t s3_pci_read(int func, int addr)
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return 0;
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}
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void s3_pci_write(int func, int addr, uint8_t val)
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void s3_pci_write(int func, int addr, uint8_t val, void *priv)
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{
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switch (addr)
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{
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@ -1482,28 +1499,28 @@ int s3_init()
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vrammask = 0x3fffff;
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io_sethandler(0x42e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL);
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io_sethandler(0x46e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL);
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io_sethandler(0x4ae8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL);
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io_sethandler(0x82e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL);
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io_sethandler(0x86e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL);
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io_sethandler(0x8ae8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL);
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io_sethandler(0x8ee8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL);
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io_sethandler(0x92e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL);
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io_sethandler(0x96e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL);
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io_sethandler(0x9ae8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL);
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io_sethandler(0x9ee8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL);
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io_sethandler(0xa2e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL);
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io_sethandler(0xa6e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL);
|
||||
io_sethandler(0xaae8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL);
|
||||
io_sethandler(0xaee8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL);
|
||||
io_sethandler(0xb2e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL);
|
||||
io_sethandler(0xb6e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL);
|
||||
io_sethandler(0xbae8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL);
|
||||
io_sethandler(0xbee8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL);
|
||||
io_sethandler(0xe2e8, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, s3_accel_out_w, s3_accel_out_l);
|
||||
io_sethandler(0x42e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, NULL);
|
||||
io_sethandler(0x46e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, NULL);
|
||||
io_sethandler(0x4ae8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, NULL);
|
||||
io_sethandler(0x82e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, NULL);
|
||||
io_sethandler(0x86e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, NULL);
|
||||
io_sethandler(0x8ae8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, NULL);
|
||||
io_sethandler(0x8ee8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, NULL);
|
||||
io_sethandler(0x92e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, NULL);
|
||||
io_sethandler(0x96e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, NULL);
|
||||
io_sethandler(0x9ae8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, NULL);
|
||||
io_sethandler(0x9ee8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, NULL);
|
||||
io_sethandler(0xa2e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, NULL);
|
||||
io_sethandler(0xa6e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, NULL);
|
||||
io_sethandler(0xaae8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, NULL);
|
||||
io_sethandler(0xaee8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, NULL);
|
||||
io_sethandler(0xb2e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, NULL);
|
||||
io_sethandler(0xb6e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, NULL);
|
||||
io_sethandler(0xbae8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, NULL);
|
||||
io_sethandler(0xbee8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, NULL);
|
||||
io_sethandler(0xe2e8, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, s3_accel_out_w, s3_accel_out_l, NULL);
|
||||
|
||||
pci_add(s3_pci_read, s3_pci_write);
|
||||
pci_add(s3_pci_read, s3_pci_write, NULL);
|
||||
|
||||
svga_vram_limit = 4 << 20; /*4mb - 864 supports 8mb but buggy VESA driver reports 0mb*/
|
||||
return svga_init();
|
||||
|
|
|
|||
Loading…
Reference in a new issue