Now up to date with current dev version.
Changes since v0.7 : - Major CPU reorganisation. This has possibly broken some stuff, though I fixed all the regressions I could find - Lazy flags. This brought 10% speed improvement at one point, but that's probably been lost now - 430 VX chipset emulation - IDT Winchip emulation (currently sans MMX). Timing is probably wrong - Fixed a few FPU bugs - Timer reorganisation - Sound reorganisation - Other general reorganisation - AdLib Gold emulation - Windows Sound System emulation - Pro Audio Spectrum 16 emulation. This currently works with most DOS stuff, but not in Windows - Major improvements to GUS emulation. Has the downside that it now conflicts with SB emulation, so probably best to not enable both simultaneously - New graphics cards : - ATI-18800 (VGA Edge-16) - ATI-28800 (VGA Charger) - ATI Mach64GX (Graphics Pro Turbo). Quite a few features missing, but Windows doesn't seem to use half the features of this card - Cirrus Logic CL-GD5429. Blitter is a bit broken - Oak OTI-067 - S3 Trio64 (Number Nine 9FX) - S3 Virge. Only framebuffer stuff at the minute, Windows won't recognise the card - Trident TGUI-9440 - VGA. Doesn't work yet - Beginnings of 3DFX emulation, however this is in extremely early stages and doesn't do anything useful - Fixed DMA bug stopping floppy drives working in Windows 3.x - Fixed some other stuff probably - Broke some other stuff probably as well
This commit is contained in:
TomW
parent
3c253c2cf8
commit
9312de19ac
87 changed files with 4528 additions and 9373 deletions
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@ -5,6 +5,8 @@
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*/
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#include "ibm.h"
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#include "io.h"
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#include "pci.h"
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#include "video.h"
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#include "vid_svga.h"
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#include "vid_icd2061.h"
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@ -15,14 +17,14 @@ int et4k_b8000;
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void et4000w32p_recalcmapping();
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uint8_t et4000w32p_mmu_read(uint32_t addr);
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void et4000w32p_mmu_write(uint32_t addr, uint8_t val);
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uint8_t et4000w32p_mmu_read(uint32_t addr, void *priv);
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void et4000w32p_mmu_write(uint32_t addr, uint8_t val, void *priv);
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static int et4000w32p_index;
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static uint8_t et4000w32p_regs[256];
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static uint32_t et4000w32p_linearbase, et4000w32p_linearbase_old;
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void et4000w32p_out(uint16_t addr, uint8_t val)
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void et4000w32p_out(uint16_t addr, uint8_t val, void *priv)
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{
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uint8_t old;
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@ -39,7 +41,7 @@ void et4000w32p_out(uint16_t addr, uint8_t val)
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break;
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case 0x3C6: case 0x3C7: case 0x3C8: case 0x3C9:
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stg_ramdac_out(addr,val);
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stg_ramdac_out(addr, val, NULL);
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return;
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case 0x3CB: /*Banking extension*/
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@ -111,10 +113,10 @@ void et4000w32p_out(uint16_t addr, uint8_t val)
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return;
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}
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svga_out(addr,val);
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svga_out(addr, val, NULL);
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}
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uint8_t et4000w32p_in(uint16_t addr)
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uint8_t et4000w32p_in(uint16_t addr, void *priv)
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{
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uint8_t temp;
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// if (addr==0x3DA) pclog("In 3DA %04X(%06X):%04X\n",CS,cs,pc);
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@ -132,7 +134,7 @@ uint8_t et4000w32p_in(uint16_t addr)
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break;
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case 0x3C6: case 0x3C7: case 0x3C8: case 0x3C9:
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return stg_ramdac_in(addr);
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return stg_ramdac_in(addr, NULL);
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case 0x3CB:
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return svgaseg2;
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@ -166,15 +168,14 @@ uint8_t et4000w32p_in(uint16_t addr)
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}
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return et4000w32p_regs[et4000w32p_index];
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}
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return svga_in(addr);
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return svga_in(addr, NULL);
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}
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void et4000w32p_recalctimings()
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{
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double clk;
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// pclog("Recalc %08X ",svga_ma);
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svga_ma|=(crtc[0x33]&0x7)<<16;
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pclog("SVGA_MA %08X %i\n", svga_ma, (svga_miscout >> 2) & 3);
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// pclog("SVGA_MA %08X %i\n", svga_ma, (svga_miscout >> 2) & 3);
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if (crtc[0x35]&2) svga_vtotal+=0x400;
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if (crtc[0x35]&4) svga_dispend+=0x400;
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if (crtc[0x35]&8) svga_vsyncstart+=0x400;
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@ -205,12 +206,12 @@ void et4000w32p_recalcmapping()
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{
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int map;
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mem_removehandler(et4000w32p_linearbase_old, 0x200000, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear);
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mem_removehandler(0xa0000, 0x20000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel);
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mem_removehandler(0xb0000, 0x10000, et4000w32p_mmu_read, NULL, NULL, et4000w32p_mmu_write, NULL, NULL);
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mem_removehandler(et4000w32p_linearbase_old, 0x200000, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, NULL);
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mem_removehandler( 0xa0000, 0x20000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, NULL);
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mem_removehandler( 0xb0000, 0x10000, et4000w32p_mmu_read, NULL, NULL, et4000w32p_mmu_write, NULL, NULL, NULL);
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if (crtc[0x36] & 0x10) /*Linear frame buffer*/
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{
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mem_sethandler(et4000w32p_linearbase, 0x200000, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear);
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mem_sethandler(et4000w32p_linearbase, 0x200000, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, NULL);
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}
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else
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{
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@ -220,28 +221,28 @@ void et4000w32p_recalcmapping()
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switch (map)
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{
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case 0x0: case 0x4: case 0x8: case 0xC: /*128k at A0000*/
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mem_sethandler(0xa0000, 0x20000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel);
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mem_sethandler(0xa0000, 0x20000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, NULL);
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break;
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case 0x1: /*64k at A0000*/
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mem_sethandler(0xa0000, 0x10000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel);
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mem_sethandler(0xa0000, 0x10000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, NULL);
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break;
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case 0x2: /*32k at B0000*/
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mem_sethandler(0xb0000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel);
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mem_sethandler(0xb0000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, NULL);
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break;
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case 0x3: /*32k at B8000*/
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mem_sethandler(0xb8000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel);
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mem_sethandler(0xb8000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, NULL);
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break;
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case 0x5: case 0x9: case 0xD: /*64k at A0000, MMU at B8000*/
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mem_sethandler(0xa0000, 0x10000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel);
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mem_sethandler(0xb8000, 0x08000, et4000w32p_mmu_read, NULL, NULL, et4000w32p_mmu_write, NULL, NULL);
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mem_sethandler(0xa0000, 0x10000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, NULL);
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mem_sethandler(0xb8000, 0x08000, et4000w32p_mmu_read, NULL, NULL, et4000w32p_mmu_write, NULL, NULL, NULL);
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break;
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case 0x6: case 0xA: case 0xE: /*32k at B0000, MMU at A8000*/
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mem_sethandler(0xa8000, 0x08000, et4000w32p_mmu_read, NULL, NULL, et4000w32p_mmu_write, NULL, NULL);
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mem_sethandler(0xb0000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel);
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mem_sethandler(0xa8000, 0x08000, et4000w32p_mmu_read, NULL, NULL, et4000w32p_mmu_write, NULL, NULL, NULL);
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mem_sethandler(0xb0000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, NULL);
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break;
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case 0x7: case 0xB: case 0xF: /*32k at B8000, MMU at A8000*/
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mem_sethandler(0xa8000, 0x08000, et4000w32p_mmu_read, NULL, NULL, et4000w32p_mmu_write, NULL, NULL);
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mem_sethandler(0xb8000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel);
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mem_sethandler(0xa8000, 0x08000, et4000w32p_mmu_read, NULL, NULL, et4000w32p_mmu_write, NULL, NULL, NULL);
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mem_sethandler(0xb8000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, NULL);
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break;
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}
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// pclog("ET4K map %02X\n", map);
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@ -295,7 +296,7 @@ void et4000w32_reset()
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void et4000w32_blit_start();
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void et4000w32_blit(int count, uint32_t mix, uint32_t sdat, int cpu_input);
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void et4000w32p_mmu_write(uint32_t addr, uint8_t val)
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void et4000w32p_mmu_write(uint32_t addr, uint8_t val, void *priv)
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{
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int bank;
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// pclog("ET4K write %08X %02X %02X %04X(%08X):%08X\n",addr,val,acl.status,acl.internal.ctrl_routing,CS,cs,pc);
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}
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}
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uint8_t et4000w32p_mmu_read(uint32_t addr)
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uint8_t et4000w32p_mmu_read(uint32_t addr, void *priv)
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{
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int bank;
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uint8_t temp;
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@ -482,6 +483,7 @@ uint8_t et4000w32p_mmu_read(uint32_t addr)
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}
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return 0xFF;
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}
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return 0xff;
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}
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int et4000w32_max_x[8]={0,0,4,8,16,32,64,0x70000000};
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@ -846,7 +848,7 @@ void et4000w32p_cursor_draw(int displine)
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svga_hwcursor_latch.addr += 16;
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}
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uint8_t et4000w32p_pci_read(int func, int addr)
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uint8_t et4000w32p_pci_read(int func, int addr, void *priv)
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{
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pclog("ET4000 PCI read %08X\n", addr);
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switch (addr)
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@ -880,7 +882,7 @@ uint8_t et4000w32p_pci_read(int func, int addr)
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return 0;
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}
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void et4000w32p_pci_write(int func, int addr, uint8_t val)
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void et4000w32p_pci_write(int func, int addr, uint8_t val, void *priv)
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{
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switch (addr)
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{
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@ -893,16 +895,16 @@ int et4000w32p_init()
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svga_recalctimings_ex = et4000w32p_recalctimings;
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svga_hwcursor_draw = et4000w32p_cursor_draw;
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io_sethandler(0x210A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL);
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io_sethandler(0x211A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL);
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io_sethandler(0x212A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL);
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io_sethandler(0x213A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL);
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io_sethandler(0x214A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL);
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io_sethandler(0x215A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL);
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io_sethandler(0x216A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL);
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io_sethandler(0x217A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL);
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io_sethandler(0x210A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, NULL);
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io_sethandler(0x211A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, NULL);
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io_sethandler(0x212A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, NULL);
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io_sethandler(0x213A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, NULL);
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io_sethandler(0x214A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, NULL);
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io_sethandler(0x215A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, NULL);
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io_sethandler(0x216A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, NULL);
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io_sethandler(0x217A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, NULL);
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pci_add(et4000w32p_pci_read, et4000w32p_pci_write);
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pci_add(et4000w32p_pci_read, et4000w32p_pci_write, NULL);
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svga_vram_limit = 2 << 20; /*2mb - chip supports 4mb but can't map both 4mb linear frame buffer and accelerator registers*/
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