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Added recompiled versions of SHL, SHR, SAR, SHLD and SHRD.

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This commit is contained in:
SarahW 2018-08-16 21:44:41 +01:00
commit 872a2da788
18 changed files with 1923 additions and 20 deletions
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208
src/codegen_backend_arm_uops.c
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@ -635,10 +635,10 @@ static int codegen_OR(codeblock_t *block, uop_t *uop)
{
host_arm_ORR_REG_LSL(block, dest_reg, src_reg_a, src_reg_b, 0);
}
else if (REG_IS_W(dest_size) && REG_IS_W(src_size_a) && REG_IS_W(src_size_b) && dest_reg == src_reg_a)
else if (REG_IS_W(dest_size) && REG_IS_W(src_size_a) && REG_IS_W(src_size_b))
{
host_arm_UXTH(block, REG_TEMP, src_reg_b, 0);
host_arm_ORR_REG_LSL(block, dest_reg, src_reg_a, REG_TEMP, 0);
host_arm_ORR_REG_LSL(block, REG_TEMP, src_reg_a, src_reg_b, 0);
host_arm_BFI(block, dest_reg, REG_TEMP, 0, 16);
}
else if (REG_IS_B(dest_size) && REG_IS_B(src_size_a) && REG_IS_B(src_size_b) && dest_reg == src_reg_a)
{
@ -692,6 +692,201 @@ static int codegen_OR_IMM(codeblock_t *block, uop_t *uop)
return 0;
}
static int codegen_SAR(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real), src_reg = HOST_REG_GET(uop->src_reg_a_real), shift_reg = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real), src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(dest_size) && REG_IS_L(src_size))
{
host_arm_MOV_REG_ASR_REG(block, dest_reg, src_reg, shift_reg);
}
else if (REG_IS_W(dest_size) && REG_IS_W(src_size))
{
host_arm_MOV_REG_LSL(block, REG_TEMP, src_reg, 16);
host_arm_MOV_REG_ASR_REG(block, REG_TEMP, REG_TEMP, shift_reg);
host_arm_UXTH(block, REG_TEMP, REG_TEMP, 16);
host_arm_BFI(block, dest_reg, REG_TEMP, 0, 16);
}
else if (REG_IS_B(dest_size) && REG_IS_B(src_size))
{
host_arm_MOV_REG_LSL(block, REG_TEMP, src_reg, 24);
host_arm_MOV_REG_ASR_REG(block, REG_TEMP, REG_TEMP, shift_reg);
host_arm_UXTB(block, REG_TEMP, REG_TEMP, 24);
host_arm_BFI(block, dest_reg, REG_TEMP, 0, 8);
}
else if (REG_IS_BH(dest_size) && REG_IS_BH(src_size))
{
host_arm_MOV_REG_LSL(block, REG_TEMP, src_reg, 16);
host_arm_MOV_REG_ASR_REG(block, REG_TEMP, REG_TEMP, shift_reg);
host_arm_UXTB(block, REG_TEMP, REG_TEMP, 24);
host_arm_BFI(block, dest_reg, REG_TEMP, 8, 8);
}
else
fatal("SAR %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;
}
static int codegen_SAR_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real), src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real), src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(dest_size) && REG_IS_L(src_size))
{
host_arm_MOV_REG_ASR(block, dest_reg, src_reg, uop->imm_data);
}
else if (REG_IS_W(dest_size) && REG_IS_W(src_size))
{
host_arm_MOV_REG_LSL(block, REG_TEMP, src_reg, 16);
host_arm_MOV_REG_ASR(block, REG_TEMP, REG_TEMP, uop->imm_data);
host_arm_UXTH(block, REG_TEMP, REG_TEMP, 16);
host_arm_BFI(block, dest_reg, REG_TEMP, 0, 16);
}
else if (REG_IS_B(dest_size) && REG_IS_B(src_size))
{
host_arm_MOV_REG_LSL(block, REG_TEMP, src_reg, 24);
host_arm_MOV_REG_ASR(block, REG_TEMP, REG_TEMP, uop->imm_data);
host_arm_UXTB(block, REG_TEMP, REG_TEMP, 24);
host_arm_BFI(block, dest_reg, REG_TEMP, 0, 8);
}
else if (REG_IS_BH(dest_size) && REG_IS_BH(src_size))
{
host_arm_MOV_REG_LSL(block, REG_TEMP, src_reg, 16);
host_arm_MOV_REG_ASR(block, REG_TEMP, REG_TEMP, uop->imm_data);
host_arm_UXTB(block, REG_TEMP, REG_TEMP, 24);
host_arm_BFI(block, dest_reg, REG_TEMP, 8, 8);
}
else
fatal("SAR_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;
}
static int codegen_SHL(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real), src_reg = HOST_REG_GET(uop->src_reg_a_real), shift_reg = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real), src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(dest_size) && REG_IS_L(src_size))
{
host_arm_MOV_REG_LSL_REG(block, dest_reg, src_reg, shift_reg);
}
else if (REG_IS_W(dest_size) && REG_IS_W(src_size))
{
host_arm_MOV_REG_LSL_REG(block, REG_TEMP, src_reg, shift_reg);
host_arm_BFI(block, dest_reg, REG_TEMP, 0, 16);
}
else if (REG_IS_B(dest_size) && REG_IS_B(src_size))
{
host_arm_MOV_REG_LSL_REG(block, REG_TEMP, src_reg, shift_reg);
host_arm_BFI(block, dest_reg, REG_TEMP, 0, 8);
}
else if (REG_IS_BH(dest_size) && REG_IS_BH(src_size))
{
host_arm_UXTB(block, REG_TEMP, src_reg, 8);
host_arm_MOV_REG_LSL_REG(block, REG_TEMP, REG_TEMP, shift_reg);
host_arm_BFI(block, dest_reg, REG_TEMP, 8, 8);
}
else
fatal("SHL %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;
}
static int codegen_SHL_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real), src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real), src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(dest_size) && REG_IS_L(src_size))
{
host_arm_MOV_REG_LSL(block, dest_reg, src_reg, uop->imm_data);
}
else if (REG_IS_W(dest_size) && REG_IS_W(src_size))
{
host_arm_MOV_REG_LSL(block, REG_TEMP, src_reg, uop->imm_data);
host_arm_BFI(block, dest_reg, REG_TEMP, 0, 16);
}
else if (REG_IS_B(dest_size) && REG_IS_B(src_size))
{
host_arm_MOV_REG_LSL(block, REG_TEMP, src_reg, uop->imm_data);
host_arm_BFI(block, dest_reg, REG_TEMP, 0, 8);
}
else if (REG_IS_BH(dest_size) && REG_IS_BH(src_size))
{
host_arm_UXTB(block, REG_TEMP, src_reg, 8);
host_arm_MOV_REG_LSL(block, REG_TEMP, REG_TEMP, uop->imm_data);
host_arm_BFI(block, dest_reg, REG_TEMP, 8, 8);
}
else
fatal("SHL_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;
}
static int codegen_SHR(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real), src_reg = HOST_REG_GET(uop->src_reg_a_real), shift_reg = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real), src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(dest_size) && REG_IS_L(src_size))
{
host_arm_MOV_REG_LSR_REG(block, dest_reg, src_reg, shift_reg);
}
else if (REG_IS_W(dest_size) && REG_IS_W(src_size))
{
host_arm_UXTH(block, REG_TEMP, src_reg, 0);
host_arm_MOV_REG_LSR_REG(block, REG_TEMP, REG_TEMP, shift_reg);
host_arm_BFI(block, dest_reg, REG_TEMP, 0, 16);
}
else if (REG_IS_B(dest_size) && REG_IS_B(src_size))
{
host_arm_UXTB(block, REG_TEMP, src_reg, 0);
host_arm_MOV_REG_LSR_REG(block, REG_TEMP, REG_TEMP, shift_reg);
host_arm_BFI(block, dest_reg, REG_TEMP, 0, 8);
}
else if (REG_IS_BH(dest_size) && REG_IS_BH(src_size))
{
host_arm_UXTB(block, REG_TEMP, src_reg, 8);
host_arm_MOV_REG_LSR_REG(block, REG_TEMP, REG_TEMP, shift_reg);
host_arm_BFI(block, dest_reg, REG_TEMP, 8, 8);
}
else
fatal("SHR %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;
}
static int codegen_SHR_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real), src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real), src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(dest_size) && REG_IS_L(src_size))
{
host_arm_MOV_REG_LSR(block, dest_reg, src_reg, uop->imm_data);
}
else if (REG_IS_W(dest_size) && REG_IS_W(src_size))
{
host_arm_UXTH(block, REG_TEMP, src_reg, 0);
host_arm_MOV_REG_LSR(block, REG_TEMP, REG_TEMP, uop->imm_data);
host_arm_BFI(block, dest_reg, REG_TEMP, 0, 16);
}
else if (REG_IS_B(dest_size) && REG_IS_B(src_size))
{
host_arm_UXTB(block, REG_TEMP, src_reg, 0);
host_arm_MOV_REG_LSR(block, REG_TEMP, REG_TEMP, uop->imm_data);
host_arm_BFI(block, dest_reg, REG_TEMP, 0, 8);
}
else if (REG_IS_BH(dest_size) && REG_IS_BH(src_size))
{
host_arm_UXTB(block, REG_TEMP, src_reg, 8);
host_arm_MOV_REG_LSR(block, REG_TEMP, REG_TEMP, uop->imm_data);
host_arm_BFI(block, dest_reg, REG_TEMP, 8, 8);
}
else
fatal("SHR_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;
}
static int codegen_STORE_PTR_IMM(codeblock_t *block, uop_t *uop)
{
host_arm_MOV_IMM(block, REG_R0, uop->imm_data);
@ -911,6 +1106,13 @@ const uOpFn uop_handlers[UOP_MAX] =
[UOP_XOR & UOP_MASK] = codegen_XOR,
[UOP_XOR_IMM & UOP_MASK] = codegen_XOR_IMM,
[UOP_SAR & UOP_MASK] = codegen_SAR,
[UOP_SAR_IMM & UOP_MASK] = codegen_SAR_IMM,
[UOP_SHL & UOP_MASK] = codegen_SHL,
[UOP_SHL_IMM & UOP_MASK] = codegen_SHL_IMM,
[UOP_SHR & UOP_MASK] = codegen_SHR,
[UOP_SHR_IMM & UOP_MASK] = codegen_SHR_IMM,
[UOP_CMP_IMM_JZ & UOP_MASK] = codegen_CMP_IMM_JZ
};