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Added waitstates on instruction fetch from ROM.

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This commit is contained in:
SarahW 2018-03-11 11:03:20 +00:00
commit 8546ce14f0
5 changed files with 38 additions and 30 deletions
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12
src/cpu.c
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@ -82,7 +82,7 @@ int cpu_cyrix_alignment;
uint64_t cpu_CR4_mask;
int cpu_cycles_read, cpu_cycles_read_l, cpu_cycles_write, cpu_cycles_write_l;
int cpu_prefetch_cycles, cpu_prefetch_width;
int cpu_prefetch_cycles, cpu_prefetch_width, cpu_mem_prefetch_cycles, cpu_rom_prefetch_cycles;
int cpu_waitstates;
int cpu_cache_int_enabled, cpu_cache_ext_enabled;
@ -508,6 +508,8 @@ void cpu_set()
cpu_update_waitstates();
isa_cycles = cpu_s->atclk_div;
cpu_rom_prefetch_cycles = cpu_s->rspeed / 1000000;
if (cpu_s->pci_speed)
{
@ -1627,7 +1629,10 @@ void cpu_update_waitstates()
{
cpu_s = &models[model].cpu[cpu_manufacturer].cpus[cpu];
cpu_prefetch_width = cpu_16bitbus ? 2 : 4;
if (is486)
cpu_prefetch_width = 16;
else
cpu_prefetch_width = cpu_16bitbus ? 2 : 4;
if (cpu_cache_int_enabled)
{
@ -1661,4 +1666,7 @@ void cpu_update_waitstates()
cpu_cycles_write = cpu_s->mem_write_cycles;
cpu_cycles_write_l = (cpu_16bitbus ? 2 : 1) * cpu_s->mem_write_cycles;
}
if (is486)
cpu_prefetch_cycles *= 4;
cpu_mem_prefetch_cycles = cpu_prefetch_cycles;
}