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Changed timer base frequency on XT models to 14.318MHz - PIT, CGA and 4.77MHz CPU should now stay in perfect sync.

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This commit is contained in:
TomW 2015-11-25 21:50:38 +00:00
commit 79202cc5c0
10 changed files with 49 additions and 29 deletions
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19
src/pc.c
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@ -182,7 +182,10 @@ void pc_reset()
pit_reset();
serial_reset();
setpitclock(models[model].cpu[cpu_manufacturer].cpus[cpu].rspeed);
if (AT)
setpitclock(models[model].cpu[cpu_manufacturer].cpus[cpu].rspeed);
else
setpitclock(14318184.0);
// sb_reset();
@ -463,7 +466,10 @@ void fullspeed()
if (!atfullspeed)
{
printf("Set fullspeed - %i %i %i\n",is386,AT,cpuspeed2);
setpitclock(models[model].cpu[cpu_manufacturer].cpus[cpu].rspeed);
if (AT)
setpitclock(models[model].cpu[cpu_manufacturer].cpus[cpu].rspeed);
else
setpitclock(14318184.0);
// if (is386) setpitclock(clocks[2][cpuspeed2][0]);
// else setpitclock(clocks[AT?1:0][cpuspeed2][0]);
}
@ -473,13 +479,10 @@ void fullspeed()
void speedchanged()
{
if (atfullspeed)
{
cpuspeed2=cpuspeed;
if (AT)
setpitclock(models[model].cpu[cpu_manufacturer].cpus[cpu].rspeed);
// if (is386) setpitclock(clocks[2][cpuspeed2][0]);
// else setpitclock(clocks[AT?1:0][cpuspeed2][0]);
}
else
setpitclock(14318184.0);
mem_updatecache();
nvr_recalc();
}