diff --git a/src/808x.c b/src/808x.c index 09e688f..04a6a9a 100644 --- a/src/808x.c +++ b/src/808x.c @@ -487,8 +487,6 @@ void makeznptable() if (!c) znptable16[c]|=Z_FLAG; if (c&0x8000) znptable16[c]|=N_FLAG; } -// isram[0xF]=1; -// printf("isram 0 = %i\n",isram[0]); // makemod1table(); } @@ -661,6 +659,7 @@ void resetx86() loadcs(0xFFFF); rammask=0xFFFFFFFF; flags=2; + makeznptable(); initmmucache(); resetreadlookup(); makemod1table(); diff --git a/src/ali1429.c b/src/ali1429.c index 2ced211..5a156c2 100644 --- a/src/ali1429.c +++ b/src/ali1429.c @@ -12,44 +12,43 @@ static uint8_t ali1429_regs[256]; void ali1429_write(uint16_t port, uint8_t val, void *priv) { // return; - if (!(port&1)) ali1429_index=val; + if (!(port & 1)) + ali1429_index = val; else { - ali1429_regs[ali1429_index]=val; + ali1429_regs[ali1429_index] = val; // pclog("ALI1429 write %02X %02X %04X:%04X %i\n",ali1429_index,val,CS,pc,ins); switch (ali1429_index) { case 0x13: -/* if (val == 1) - { - times = 1; - ins = 0; - output = 3; - }*/ -// pclog("write 13 %02X %i\n",val,shadowbios); - if (!(val&0xC0)) - { - shadowbios=0; - if (!shadowbios_write) - mem_sethandler(0xf0000, 0x10000, mem_read_bios, mem_read_biosw, mem_read_biosl, NULL, NULL, NULL, NULL); - else - mem_sethandler(0xf0000, 0x10000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); - flushmmucache(); - } - break; + if (!(val & 0xc0)) + { + shadowbios = 0; + if (!shadowbios_write) + mem_bios_set_state(0xf0000, 0x10000, 0, 0); + else + mem_bios_set_state(0xf0000, 0x10000, 0, 1); + flushmmucache(); + } + break; case 0x14: - shadowbios=val&1;//((val&3)==1); - shadowbios_write=val&2; + shadowbios = val & 1; + shadowbios_write = val & 2; switch (val & 3) { - case 0: mem_sethandler(0xf0000, 0x10000, mem_read_bios, mem_read_biosw, mem_read_biosl, NULL, NULL, NULL, NULL); break; - case 1: mem_sethandler(0xf0000, 0x10000, mem_read_ram, mem_read_ramw, mem_read_raml, NULL, NULL, NULL, NULL); break; - case 2: mem_sethandler(0xf0000, 0x10000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); break; - case 3: mem_sethandler(0xf0000, 0x10000, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); break; + case 0: + mem_bios_set_state(0xf0000, 0x10000, 0, 0); + break; + case 1: + mem_bios_set_state(0xf0000, 0x10000, 1, 0); + break; + case 2: + mem_bios_set_state(0xf0000, 0x10000, 0, 1); + break; + case 3: + mem_bios_set_state(0xf0000, 0x10000, 1, 1); + break; } - -// if (val==0x43) shadowbios=1; -// pclog("Shadow bios %i\n",shadowbios); flushmmucache(); break; } @@ -58,16 +57,17 @@ void ali1429_write(uint16_t port, uint8_t val, void *priv) uint8_t ali1429_read(uint16_t port, void *priv) { - if (!(port&1)) return ali1429_index; + if (!(port & 1)) + return ali1429_index; if ((ali1429_index >= 0xc0 || ali1429_index == 0x20) && cpu_iscyrix) - return 0xff; /*Don't conflict with Cyrix config registers*/ + return 0xff; /*Don't conflict with Cyrix config registers*/ return ali1429_regs[ali1429_index]; } void ali1429_reset() { - memset(ali1429_regs,0xFF,256); + memset(ali1429_regs, 0xff, 256); } void ali1429_init() diff --git a/src/dma.c b/src/dma.c index 766354d..b679589 100644 --- a/src/dma.c +++ b/src/dma.c @@ -3,6 +3,7 @@ #include "dma.h" #include "fdc.h" #include "io.h" +#include "mem.h" #include "video.h" extern int ins; @@ -256,39 +257,12 @@ void dma16_init() uint8_t _dma_read(uint32_t addr) { - switch (addr&0xFFFF8000) - { -/* case 0xA0000: case 0xA8000: - return video_read_a000(addr, NULL); - case 0xB0000: - return video_read_b000(addr, NULL); - case 0xB8000: - return video_read_b800(addr, NULL);*/ - } - if (isram[addr>>16]) return ram[addr]; - return 0xff; + return mem_readb_phys(addr); } void _dma_write(uint32_t addr, uint8_t val) { - pclog("_dma_write %08X %02X\n", addr, val); - switch (addr&0xFFFF8000) - { -/* case 0xA0000: case 0xA8000: - video_write_a000(addr,val, NULL); - return; - case 0xB0000: - video_write_b000(addr,val, NULL); - return; - case 0xB8000: - video_write_b800(addr,val, NULL); - return; - case 0xC0000: case 0xC8000: case 0xD0000: case 0xD8000: - case 0xE0000: case 0xE8000: case 0xF0000: case 0xF8000: - return;*/ - } - if (isram[addr >> 16]) - ram[addr] = val; + mem_writeb_phys(addr, val); } /*void writedma2(uint8_t val) { diff --git a/src/headland.c b/src/headland.c index c7e9312..d6fae72 100644 --- a/src/headland.c +++ b/src/headland.c @@ -20,12 +20,13 @@ void headland_write(uint16_t addr, uint8_t val, void *priv) shadowbios = val & 0x10; shadowbios_write = !(val & 0x10); if (shadowbios) - mem_sethandler(0xf0000, 0x10000, mem_read_ram, mem_read_ramw, mem_read_raml, NULL, NULL, NULL , NULL); + mem_bios_set_state(0xf0000, 0x10000, 1, 0); else - mem_sethandler(0xf0000, 0x10000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); + mem_bios_set_state(0xf0000, 0x10000, 0, 1); } } - else headland_index = val; + else + headland_index = val; } uint8_t headland_read(uint16_t addr, void *priv) @@ -33,7 +34,7 @@ uint8_t headland_read(uint16_t addr, void *priv) if (addr & 1) { if ((headland_index >= 0xc0 || headland_index == 0x20) && cpu_iscyrix) - return 0xff; /*Don't conflict with Cyrix config registers*/ + return 0xff; /*Don't conflict with Cyrix config registers*/ return headland_regs[headland_index]; } return headland_index; diff --git a/src/i430vx.c b/src/i430vx.c index df4d8f7..f058ccc 100644 --- a/src/i430vx.c +++ b/src/i430vx.c @@ -13,10 +13,10 @@ static void i430vx_map(uint32_t addr, uint32_t size, int state) { switch (state & 3) { - case 0x0: mem_sethandler(addr, size, mem_read_bios, mem_read_biosw, mem_read_biosl, NULL, NULL, NULL , NULL); break; /*DRAM disabled, accesses directed to PCI bus*/ - case 0x1: mem_sethandler(addr, size, mem_read_ram, mem_read_ramw, mem_read_raml, NULL, NULL, NULL , NULL); break; /*Read only, DRAM write protected, non-cacheable*/ - case 0x2: mem_sethandler(addr, size, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); break; /*Write only*/ - case 0x3: mem_sethandler(addr, size, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); break; /*Read/write, non-cacheable*/ + case 0x0: mem_bios_set_state(addr, size, 0, 0); break; /*DRAM disabled, accesses directed to PCI bus*/ + case 0x1: mem_bios_set_state(addr, size, 1, 0); break; /*Read only, DRAM write protected, non-cacheable*/ + case 0x2: mem_bios_set_state(addr, size, 0, 1); break; /*Write only*/ + case 0x3: mem_bios_set_state(addr, size, 1, 1); break; /*Read/write, non-cacheable*/ /*Below are redundant*/ // case 0x5: mem_sethandler(addr, size, mem_read_ram, mem_read_ramw, mem_read_raml, NULL, NULL, NULL ); break; /*Read only, DRAM write protected, cacheable*/ // case 0x7: mem_sethandler(addr, size, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml); break; /*Read/write, non-cacheable*/ diff --git a/src/ibm.h b/src/ibm.h index 2d6fb6a..de1cdf0 100644 --- a/src/ibm.h +++ b/src/ibm.h @@ -6,8 +6,6 @@ /*Memory*/ uint8_t *ram,*vram; -unsigned char isram[0x10000]; - uint32_t rammask; int readlookup[256],readlookupp[256]; diff --git a/src/mem.c b/src/mem.c index 8d00c30..ec60cb8 100644 --- a/src/mem.c +++ b/src/mem.c @@ -15,21 +15,25 @@ #include "x86.h" #include "cpu.h" -static uint8_t (*_mem_read_b[0x40000])(uint32_t addr, void *priv); -static uint16_t (*_mem_read_w[0x40000])(uint32_t addr, void *priv); -static uint32_t (*_mem_read_l[0x40000])(uint32_t addr, void *priv); -static void (*_mem_write_b[0x40000])(uint32_t addr, uint8_t val, void *priv); -static void (*_mem_write_w[0x40000])(uint32_t addr, uint16_t val, void *priv); -static void (*_mem_write_l[0x40000])(uint32_t addr, uint32_t val, void *priv); -static void *_mem_priv[0x40000]; +static uint8_t (*_mem_read_b[0x40000])(uint32_t addr, void *priv); +static uint16_t (*_mem_read_w[0x40000])(uint32_t addr, void *priv); +static uint32_t (*_mem_read_l[0x40000])(uint32_t addr, void *priv); +static void (*_mem_write_b[0x40000])(uint32_t addr, uint8_t val, void *priv); +static void (*_mem_write_w[0x40000])(uint32_t addr, uint16_t val, void *priv); +static void (*_mem_write_l[0x40000])(uint32_t addr, uint32_t val, void *priv); +static void *_mem_priv[0x40000]; +static mem_mapping_t *_mem_mapping[0x40000]; + +static mem_mapping_t base_mapping; +static mem_mapping_t ram_low_mapping; +static mem_mapping_t ram_high_mapping; +static mem_mapping_t bios_mapping[8]; +static mem_mapping_t vrom_mapping; +static mem_mapping_t romext_mapping; int shadowbios,shadowbios_write; -uint32_t oldpc; -extern uint8_t opcode2; -unsigned char isram[0x10000]; -extern int ins; -extern int timetolive; +static unsigned char isram[0x10000]; int mem_size; int cache=4; @@ -1252,6 +1256,20 @@ void writememll(uint32_t seg, uint32_t addr, uint32_t val) // pclog("Bad write %08X %08X\n", addr2, val); } +uint8_t mem_readb_phys(uint32_t addr) +{ + if (_mem_read_b[addr >> 14]) + return _mem_read_b[addr >> 14](addr, _mem_priv[addr >> 14]); + + return 0xff; +} + +void mem_writeb_phys(uint32_t addr, uint8_t val) +{ + if (_mem_write_b[addr >> 14]) + _mem_write_b[addr >> 14](addr, val, _mem_priv[addr >> 14]); +} + uint8_t mem_read_ram(uint32_t addr, void *priv) { // if (addr >= 0xe0000 && addr < 0x100000) pclog("Read RAMb %08X\n", addr); @@ -1338,62 +1356,6 @@ uint32_t mem_read_romextl(uint32_t addr, void *priv) return *(uint32_t *)&romext[addr & 0x7fff]; } -void mem_init() -{ - int c; - ram=malloc(mem_size*1024*1024); - rom=malloc(0x20000); - vram=malloc(0x800000); - vrom=malloc(0x8000); - readlookup2=malloc(1024*1024*4); - writelookup2=malloc(1024*1024*4); - cachelookup2=malloc(1024*1024); - biosmask=65535; - makeznptable(); - memset(ram,0,mem_size*1024*1024); - for (c = 0; c < 0x10000; c++) isram[c] = 0; - for (c=0;c<(mem_size*16);c++) - { - isram[c]=1; - if (c >= 0xa && c<=0xF) isram[c]=0; - } - for (c = 0; c < 0x40000; c++) - _mem_read_b[c] = _mem_read_w[c] = _mem_read_l[c] = _mem_write_b[c] = _mem_write_w[c] = _mem_write_l[c] = _mem_priv[c] = NULL; - - mem_sethandler(0x00000, 0xa0000, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); - if (mem_size > 1) - mem_sethandler(0x100000, (mem_size - 1) * 1024 * 1024, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); - - mem_sethandler(0xc0000, 0x08000, mem_read_vrom, mem_read_vromw, mem_read_vroml, NULL, NULL, NULL, NULL); - mem_sethandler(0xc8000, 0x08000, mem_read_romext, mem_read_romextw, mem_read_romextl, NULL, NULL, NULL, NULL); - mem_sethandler(0xe0000, 0x20000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); -// pclog("Mem resize %i %i\n",mem_size,c); -} - -void mem_resize() -{ - int c; - free(ram); - ram=malloc(mem_size*1024*1024); - memset(ram,0,mem_size*1024*1024); - for (c = 0; c < 0x10000; c++) isram[c] = 0; - for (c=0;c<(mem_size*16);c++) - { - isram[c]=1; - if (c >= 0xa && c<=0xF) isram[c]=0; - } - for (c = 0; c < 0x40000; c++) - _mem_read_b[c] = _mem_read_w[c] = _mem_read_l[c] = _mem_write_b[c] = _mem_write_w[c] = _mem_write_l[c] = _mem_priv[c] = NULL; - - mem_sethandler(0x00000, 0xa0000, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); - if (mem_size > 1) - mem_sethandler(0x100000, (mem_size - 1) * 1024 * 1024, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); - - mem_sethandler(0xc0000, 0x8000, mem_read_vrom, mem_read_vromw, mem_read_vroml, NULL, NULL, NULL, NULL); - mem_sethandler(0xc8000, 0x8000, mem_read_romext, mem_read_romextw, mem_read_romextl, NULL, NULL, NULL, NULL); - mem_sethandler(0xe0000, 0x20000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); -// pclog("Mem resize %i %i\n",mem_size,c); -} void mem_updatecache() { @@ -1418,63 +1380,266 @@ void mem_updatecache() } } -void mem_sethandler(uint32_t base, uint32_t size, - uint8_t (*read_b)(uint32_t addr, void *priv), - uint16_t (*read_w)(uint32_t addr, void *priv), - uint32_t (*read_l)(uint32_t addr, void *priv), - void (*write_b)(uint32_t addr, uint8_t val, void *priv), - void (*write_w)(uint32_t addr, uint16_t val, void *priv), - void (*write_l)(uint32_t addr, uint32_t val, void *priv), - void *priv) -{ - uint32_t c; -// printf("mem_sethandler : %05X %04X %08X %08X %08X %08X %08X\n", base, size, read_w, write_w, mem_read_biosw, mem_read_ramw, mem_write_ramw); - for (c = base; c < base + size; c += 0x4000) - { - _mem_read_b[ c >> 14] = read_b; - _mem_read_w[ c >> 14] = read_w; - _mem_read_l[ c >> 14] = read_l; - _mem_write_b[c >> 14] = write_b; - _mem_write_w[c >> 14] = write_w; - _mem_write_l[c >> 14] = write_l; - _mem_priv[c >> 14] = priv; - } - for (c = base; c < base + size; c += 0x1000) - { - readlookup2[c >> 12] = 0xFFFFFFFF; - writelookup2[c >> 12] = 0xFFFFFFFF; - } -} - -void mem_removehandler(uint32_t base, uint32_t size, - uint8_t (*read_b)(uint32_t addr, void *priv), - uint16_t (*read_w)(uint32_t addr, void *priv), - uint32_t (*read_l)(uint32_t addr, void *priv), - void (*write_b)(uint32_t addr, uint8_t val, void *priv), - void (*write_w)(uint32_t addr, uint16_t val, void *priv), - void (*write_l)(uint32_t addr, uint32_t val, void *priv), - void *priv) +static void mem_mapping_recalc(uint32_t base, uint32_t size) { uint32_t c; + mem_mapping_t *mapping = base_mapping.next; + if ((base + size) > 0xffff8000) size = 0xffff0000 - base; + + /*Clear out old mappings*/ for (c = base; c < base + size; c += 0x4000) { - if (_mem_priv[c >> 14] == priv) - { - if ( _mem_read_b[c >> 14] == read_b) _mem_read_b[c >> 14] = NULL; - if ( _mem_read_w[c >> 14] == read_w) _mem_read_w[c >> 14] = NULL; - if ( _mem_read_l[c >> 14] == read_l) _mem_read_l[c >> 14] = NULL; - if (_mem_write_b[c >> 14] == write_b) _mem_write_b[c >> 14] = NULL; - if (_mem_write_w[c >> 14] == write_w) _mem_write_w[c >> 14] = NULL; - if (_mem_write_l[c >> 14] == write_l) _mem_write_l[c >> 14] = NULL; - _mem_priv[c >> 14] = NULL; - } + _mem_read_b[c >> 14] = NULL; + _mem_read_w[c >> 14] = NULL; + _mem_read_l[c >> 14] = NULL; + _mem_write_b[c >> 14] = NULL; + _mem_write_w[c >> 14] = NULL; + _mem_write_l[c >> 14] = NULL; + _mem_priv[c >> 14] = NULL; + _mem_mapping[c >> 14] = NULL; } - for (c = base; c < base + size; c += 0x1000) +// pclog("mem_mapping_recalc %08X %08X\n", base, size); + /*Walk mapping list*/ + while (mapping != NULL) { - readlookup2[c >> 12] = 0xFFFFFFFF; - writelookup2[c >> 12] = 0xFFFFFFFF; +// pclog("mapping=%p next=%p base=%08X size=%08X enable=%i\n", mapping, mapping->next, mapping->base, mapping->size, mapping->enable); + /*In range?*/ + if (mapping->enable && mapping->base < (base + size) && (mapping->base + mapping->size) >= base) + { + uint32_t start = (mapping->base < base) ? mapping->base : base; + uint32_t end = ((mapping->base + mapping->size) < (base + size)) ? (mapping->base + mapping->size) : (base + size); + + for (c = start; c < end; c += 0x4000) + { + if (_mem_mapping[c >> 14] == NULL) + { +// pclog(" Add %08X\n", c); + _mem_read_b[c >> 14] = mapping->read_b; + _mem_read_w[c >> 14] = mapping->read_w; + _mem_read_l[c >> 14] = mapping->read_l; + _mem_write_b[c >> 14] = mapping->write_b; + _mem_write_w[c >> 14] = mapping->write_w; + _mem_write_l[c >> 14] = mapping->write_l; + _mem_priv[c >> 14] = mapping->p; + _mem_mapping[c >> 14] = mapping; + } + } + } + mapping = mapping->next; + } +} + +void mem_mapping_add(mem_mapping_t *mapping, + uint32_t base, + uint32_t size, + uint8_t (*read_b)(uint32_t addr, void *p), + uint16_t (*read_w)(uint32_t addr, void *p), + uint32_t (*read_l)(uint32_t addr, void *p), + void (*write_b)(uint32_t addr, uint8_t val, void *p), + void (*write_w)(uint32_t addr, uint16_t val, void *p), + void (*write_l)(uint32_t addr, uint32_t val, void *p), + void *p) +{ + mem_mapping_t *dest = &base_mapping; + + /*Add mapping to the end of the list*/ + while (dest->next) + dest = dest->next; + dest->next = mapping; + + if (size) + mapping->enable = 1; + else + mapping->enable = 0; + mapping->base = base; + mapping->size = size; + mapping->read_b = read_b; + mapping->read_w = read_w; + mapping->read_l = read_l; + mapping->write_b = write_b; + mapping->write_w = write_w; + mapping->write_l = write_l; + mapping->p = p; + mapping->next = NULL; + + mem_mapping_recalc(mapping->base, mapping->size); +} + +void mem_mapping_set_handler(mem_mapping_t *mapping, + uint8_t (*read_b)(uint32_t addr, void *p), + uint16_t (*read_w)(uint32_t addr, void *p), + uint32_t (*read_l)(uint32_t addr, void *p), + void (*write_b)(uint32_t addr, uint8_t val, void *p), + void (*write_w)(uint32_t addr, uint16_t val, void *p), + void (*write_l)(uint32_t addr, uint32_t val, void *p)) +{ + mapping->read_b = read_b; + mapping->read_w = read_w; + mapping->read_l = read_l; + mapping->write_b = write_b; + mapping->write_w = write_w; + mapping->write_l = write_l; + + mem_mapping_recalc(mapping->base, mapping->size); +} + +void mem_mapping_set_addr(mem_mapping_t *mapping, uint32_t base, uint32_t size) +{ + /*Remove old mapping*/ + mapping->enable = 0; + mem_mapping_recalc(mapping->base, mapping->size); + + /*Set new mapping*/ + mapping->enable = 1; + mapping->base = base; + mapping->size = size; + + mem_mapping_recalc(mapping->base, mapping->size); +} + +void mem_mapping_set_p(mem_mapping_t *mapping, void *p) +{ + mapping->p = p; +} + +void mem_mapping_disable(mem_mapping_t *mapping) +{ + mapping->enable = 0; + + mem_mapping_recalc(mapping->base, mapping->size); +} + +void mem_mapping_enable(mem_mapping_t *mapping) +{ + mapping->enable = 1; + + mem_mapping_recalc(mapping->base, mapping->size); +} + +void mem_init() +{ + int c; + + ram = malloc(mem_size * 1024 * 1024); + rom = malloc(0x20000); + vram = malloc(0x800000); + vrom = malloc(0x8000); + readlookup2 = malloc(1024 * 1024 * 4); + writelookup2 = malloc(1024 * 1024 * 4); + cachelookup2 = malloc(1024 * 1024); + biosmask = 0xffff; + + memset(ram, 0, mem_size * 1024 * 1024); + + memset(isram, 0, sizeof(isram)); + for (c = 0; c < (mem_size * 16); c++) + { + isram[c] = 1; + if (c >= 0xa && c <= 0xf) + isram[c] = 0; + } + + memset(_mem_read_b, 0, sizeof(_mem_read_b)); + memset(_mem_read_w, 0, sizeof(_mem_read_w)); + memset(_mem_read_l, 0, sizeof(_mem_read_l)); + memset(_mem_write_b, 0, sizeof(_mem_write_b)); + memset(_mem_write_w, 0, sizeof(_mem_write_w)); + memset(_mem_write_l, 0, sizeof(_mem_write_l)); + + memset(&base_mapping, 0, sizeof(base_mapping)); + + mem_mapping_add(&ram_low_mapping, 0x00000, 0xa0000, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); + if (mem_size > 1) + mem_mapping_add(&ram_low_mapping, 0x100000, (mem_size - 1) * 1024 * 1024, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); + + mem_mapping_add(&bios_mapping[0], 0xe0000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); + mem_mapping_add(&bios_mapping[1], 0xe4000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); + mem_mapping_add(&bios_mapping[2], 0xe8000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); + mem_mapping_add(&bios_mapping[3], 0xec000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); + mem_mapping_add(&bios_mapping[4], 0xf0000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); + mem_mapping_add(&bios_mapping[5], 0xf4000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); + mem_mapping_add(&bios_mapping[6], 0xf8000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); + mem_mapping_add(&bios_mapping[7], 0xfc000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); + + mem_mapping_add(&vrom_mapping, 0xc0000, 0x08000, mem_read_vrom, mem_read_vromw, mem_read_vroml, NULL, NULL, NULL, NULL); + mem_mapping_add(&romext_mapping, 0xc8000, 0x08000, mem_read_romext, mem_read_romextw, mem_read_romextl, NULL, NULL, NULL, NULL); +// pclog("Mem resize %i %i\n",mem_size,c); +} + +void mem_resize() +{ + int c; + + free(ram); + ram = malloc(mem_size * 1024 * 1024); + memset(ram, 0, mem_size * 1024 * 1024); + + memset(isram, 0, sizeof(isram)); + for (c = 0; c < (mem_size * 16); c++) + { + isram[c] = 1; + if (c >= 0xa && c <= 0xf) + isram[c] = 0; + } + + memset(_mem_read_b, 0, sizeof(_mem_read_b)); + memset(_mem_read_w, 0, sizeof(_mem_read_w)); + memset(_mem_read_l, 0, sizeof(_mem_read_l)); + memset(_mem_write_b, 0, sizeof(_mem_write_b)); + memset(_mem_write_w, 0, sizeof(_mem_write_w)); + memset(_mem_write_l, 0, sizeof(_mem_write_l)); + + memset(&base_mapping, 0, sizeof(base_mapping)); + + mem_mapping_add(&ram_low_mapping, 0x00000, 0xa0000, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); + if (mem_size > 1) + mem_mapping_add(&ram_low_mapping, 0x100000, (mem_size - 1) * 1024 * 1024, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); + + mem_mapping_add(&bios_mapping[0], 0xe0000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); + mem_mapping_add(&bios_mapping[1], 0xe4000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); + mem_mapping_add(&bios_mapping[2], 0xe8000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); + mem_mapping_add(&bios_mapping[3], 0xec000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); + mem_mapping_add(&bios_mapping[4], 0xf0000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); + mem_mapping_add(&bios_mapping[5], 0xf4000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); + mem_mapping_add(&bios_mapping[6], 0xf8000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); + mem_mapping_add(&bios_mapping[7], 0xfc000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); + + mem_mapping_add(&vrom_mapping, 0xc0000, 0x08000, mem_read_vrom, mem_read_vromw, mem_read_vroml, NULL, NULL, NULL, NULL); + mem_mapping_add(&romext_mapping, 0xc8000, 0x08000, mem_read_romext, mem_read_romextw, mem_read_romextl, NULL, NULL, NULL, NULL); + +// pclog("Mem resize %i %i\n",mem_size,c); +} + +void mem_bios_set_state(uint32_t base, uint32_t size, int read_ram, int write_ram) +{ + uint32_t c; + int state = (read_ram ? 1 : 0) | (write_ram ? 2: 0); + + if (base < 0xe0000 || base > 0xfffff) + return; + if ((base + size) > 0x100000) + size = 0x100000 - base; + + for (c = base; c < (base + size); c+= 0x4000) + { +// pclog("mem_bios_set_state: c=%08X base=%08X size=%08X bios=%i\n", c, base, size, (c - 0xe0000) >> 14); + switch (state) + { + case 0: + mem_mapping_set_handler(&bios_mapping[(c - 0xe0000) >> 14], mem_read_bios, mem_read_biosw, mem_read_biosl, NULL, NULL, NULL); + break; + case 1: + mem_mapping_set_handler(&bios_mapping[(c - 0xe0000) >> 14], mem_read_ram, mem_read_ramw, mem_read_raml, NULL, NULL, NULL); + break; + case 2: + mem_mapping_set_handler(&bios_mapping[(c - 0xe0000) >> 14], mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml); + break; + case 3: + mem_mapping_set_handler(&bios_mapping[(c - 0xe0000) >> 14], mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml); + break; + } } } diff --git a/src/mem.h b/src/mem.h index 139bb1c..dfafb66 100644 --- a/src/mem.h +++ b/src/mem.h @@ -1,3 +1,22 @@ +typedef struct mem_mapping_t +{ + struct mem_mapping_t *prev, *next; + + int enable; + + uint32_t base; + uint32_t size; + + uint8_t (*read_b)(uint32_t addr, void *priv); + uint16_t (*read_w)(uint32_t addr, void *priv); + uint32_t (*read_l)(uint32_t addr, void *priv); + void (*write_b)(uint32_t addr, uint8_t val, void *priv); + void (*write_w)(uint32_t addr, uint16_t val, void *priv); + void (*write_l)(uint32_t addr, uint32_t val, void *priv); + + void *p; +} mem_mapping_t; + extern uint8_t *ram,*rom,*vram,*vrom; extern uint8_t romext[32768]; extern int readlnum,writelnum; @@ -6,27 +25,37 @@ extern int nopageerrors; extern int cache; extern int memwaitstate; -void mem_sethandler(uint32_t base, uint32_t size, - uint8_t (*read_b)(uint32_t addr, void *priv), - uint16_t (*read_w)(uint32_t addr, void *priv), - uint32_t (*read_l)(uint32_t addr, void *priv), - void (*write_b)(uint32_t addr, uint8_t val, void *priv), - void (*write_w)(uint32_t addr, uint16_t val, void *priv), - void (*write_l)(uint32_t addr, uint32_t val, void *priv), - void *priv); +void mem_mapping_add(mem_mapping_t *mapping, + uint32_t base, + uint32_t size, + uint8_t (*read_b)(uint32_t addr, void *p), + uint16_t (*read_w)(uint32_t addr, void *p), + uint32_t (*read_l)(uint32_t addr, void *p), + void (*write_b)(uint32_t addr, uint8_t val, void *p), + void (*write_w)(uint32_t addr, uint16_t val, void *p), + void (*write_l)(uint32_t addr, uint32_t val, void *p), + void *p); +void mem_mapping_set_handler(mem_mapping_t *mapping, + uint8_t (*read_b)(uint32_t addr, void *p), + uint16_t (*read_w)(uint32_t addr, void *p), + uint32_t (*read_l)(uint32_t addr, void *p), + void (*write_b)(uint32_t addr, uint8_t val, void *p), + void (*write_w)(uint32_t addr, uint16_t val, void *p), + void (*write_l)(uint32_t addr, uint32_t val, void *p)); +void mem_mapping_set_p(mem_mapping_t *mapping, void *p); +void mem_mapping_set_addr(mem_mapping_t *mapping, uint32_t base, uint32_t size); +void mem_mapping_disable(mem_mapping_t *mapping); +void mem_mapping_enable(mem_mapping_t *mapping); + +void mem_bios_set_state(uint32_t base, uint32_t size, int read_ram, int write_ram); -void mem_removehandler(uint32_t base, uint32_t size, - uint8_t (*read_b)(uint32_t addr, void *priv), - uint16_t (*read_w)(uint32_t addr, void *priv), - uint32_t (*read_l)(uint32_t addr, void *priv), - void (*write_b)(uint32_t addr, uint8_t val, void *priv), - void (*write_w)(uint32_t addr, uint16_t val, void *priv), - void (*write_l)(uint32_t addr, uint32_t val, void *priv), - void *priv); extern int mem_a20_alt; extern int mem_a20_key; void mem_a20_recalc(); +uint8_t mem_readb_phys(uint32_t addr); +void mem_writeb_phys(uint32_t addr, uint8_t val); + uint8_t mem_read_ram(uint32_t addr, void *priv); uint16_t mem_read_ramw(uint32_t addr, void *priv); uint32_t mem_read_raml(uint32_t addr, void *priv); diff --git a/src/sis496.c b/src/sis496.c index 0a88836..220c390 100644 --- a/src/sis496.c +++ b/src/sis496.c @@ -17,42 +17,42 @@ void sis496_recalcmapping(sis496_t *sis496) if (sis496->pci_conf[0x44] & 0x10) { if (sis496->pci_conf[0x45] & 0x01) - mem_sethandler(0xe0000, 0x8000, mem_read_ram, mem_read_ramw, mem_read_raml, NULL, NULL, NULL, NULL); + mem_bios_set_state(0xe0000, 0x08000, 1, 0); else - mem_sethandler(0xe0000, 0x8000, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); + mem_bios_set_state(0xe0000, 0x08000, 1, 1); } else - mem_sethandler(0xe0000, 0x8000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); + mem_bios_set_state(0xe0000, 0x08000, 0, 1); if (sis496->pci_conf[0x44] & 0x20) { if (sis496->pci_conf[0x45] & 0x01) - mem_sethandler(0xe8000, 0x8000, mem_read_ram, mem_read_ramw, mem_read_raml, NULL, NULL, NULL, NULL); + mem_bios_set_state(0xe8000, 0x08000, 1, 0); else - mem_sethandler(0xe8000, 0x8000, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); + mem_bios_set_state(0xe8000, 0x08000, 1, 1); } else - mem_sethandler(0xe8000, 0x8000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); + mem_bios_set_state(0xe8000, 0x08000, 0, 1); if (sis496->pci_conf[0x44] & 0x40) { if (sis496->pci_conf[0x45] & 0x01) - mem_sethandler(0xf0000, 0x8000, mem_read_ram, mem_read_ramw, mem_read_raml, NULL, NULL, NULL, NULL); + mem_bios_set_state(0xf0000, 0x08000, 1, 0); else - mem_sethandler(0xf0000, 0x8000, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); + mem_bios_set_state(0xf0000, 0x08000, 1, 1); } else - mem_sethandler(0xf0000, 0x8000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); + mem_bios_set_state(0xf0000, 0x08000, 0, 1); if (sis496->pci_conf[0x44] & 0x80) { if (sis496->pci_conf[0x45] & 0x01) - mem_sethandler(0xf8000, 0x8000, mem_read_ram, mem_read_ramw, mem_read_raml, NULL, NULL, NULL, NULL); + mem_bios_set_state(0xf8000, 0x08000, 1, 0); else - mem_sethandler(0xf8000, 0x8000, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); + mem_bios_set_state(0xf8000, 0x08000, 1, 1); } else - mem_sethandler(0xf8000, 0x8000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); + mem_bios_set_state(0xf8000, 0x08000, 0, 1); flushmmucache(); shadowbios = (sis496->pci_conf[0x44] & 0xf0); diff --git a/src/um8881f.c b/src/um8881f.c index 0f9aa7a..a045797 100644 --- a/src/um8881f.c +++ b/src/um8881f.c @@ -15,9 +15,9 @@ void um8881f_write(int func, int addr, uint8_t val, void *priv) if ((card_16[0x54] ^ val) & 0x01) { if (val & 1) - mem_sethandler(0xe0000, 0x10000, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); + mem_bios_set_state(0xe0000, 0x10000, 1, 1); else - mem_sethandler(0xf0000, 0x10000, mem_read_bios, mem_read_biosw, mem_read_biosl, NULL, NULL, NULL , NULL); + mem_bios_set_state(0xe0000, 0x10000, 0, 0); } flushmmucache_nopc(); } @@ -27,10 +27,10 @@ void um8881f_write(int func, int addr, uint8_t val, void *priv) { switch (val & 0xc0) { - case 0x00: mem_sethandler(0xf0000, 0x10000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); break; - case 0x40: mem_sethandler(0xf0000, 0x10000, mem_read_bios, mem_read_biosw, mem_read_biosl, NULL, NULL, NULL , NULL); break; - case 0x80: mem_sethandler(0xf0000, 0x10000, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, NULL); break; - case 0xc0: mem_sethandler(0xf0000, 0x10000, mem_read_ram, mem_read_ramw, mem_read_raml, NULL, NULL, NULL , NULL); break; + case 0x00: mem_bios_set_state(0xf0000, 0x10000, 0, 1); break; + case 0x40: mem_bios_set_state(0xf0000, 0x10000, 0, 0); break; + case 0x80: mem_bios_set_state(0xf0000, 0x10000, 1, 1); break; + case 0xc0: mem_bios_set_state(0xf0000, 0x10000, 1, 0); break; } shadowbios = val & 0x80; shadowbios_write = !(val & 0x40); @@ -56,9 +56,7 @@ uint8_t um8886f_read(int func, int addr, void *priv) { return card_18[addr]; } - - - + void um8881f_init() { pci_add_specific(16, um8881f_read, um8881f_write, NULL); diff --git a/src/vid_ati18800.c b/src/vid_ati18800.c index a41d0e7..b573725 100644 --- a/src/vid_ati18800.c +++ b/src/vid_ati18800.c @@ -3,6 +3,7 @@ #include "ibm.h" #include "device.h" #include "io.h" +#include "mem.h" #include "video.h" #include "vid_ati18800.h" #include "vid_ati_eeprom.h" diff --git a/src/vid_ati28800.c b/src/vid_ati28800.c index db8f4ae..11f31ac 100644 --- a/src/vid_ati28800.c +++ b/src/vid_ati28800.c @@ -3,6 +3,7 @@ #include "ibm.h" #include "device.h" #include "io.h" +#include "mem.h" #include "video.h" #include "vid_ati28800.h" #include "vid_ati_eeprom.h" diff --git a/src/vid_ati68860_ramdac.c b/src/vid_ati68860_ramdac.c index 448756f..cf03221 100644 --- a/src/vid_ati68860_ramdac.c +++ b/src/vid_ati68860_ramdac.c @@ -19,6 +19,7 @@ bit 0 Controls 6/8bit DAC. 0: 8bit DAC/LUT, 1: 6bit DAC/LUT 7 If set can remove "snow" in some cases (A860_Delay_L ?) ?? */ #include "ibm.h" +#include "mem.h" #include "video.h" #include "vid_svga.h" #include "vid_ati68860_ramdac.h" diff --git a/src/vid_ati_mach64.c b/src/vid_ati_mach64.c index 4d7d654..e22108d 100644 --- a/src/vid_ati_mach64.c +++ b/src/vid_ati_mach64.c @@ -16,6 +16,10 @@ typedef struct mach64_t { + mem_mapping_t linear_mapping; + mem_mapping_t mmio_mapping; + mem_mapping_t mmio_linear_mapping; + ati68860_ramdac_t ramdac; ati_eeprom_t eeprom; ics2595_t ics2595; @@ -321,38 +325,43 @@ void mach64_recalctimings(svga_t *svga) void mach64_updatemapping(mach64_t *mach64) { svga_t *svga = &mach64->svga; - mem_removehandler(0xa0000, 0x10000, mach64_read, NULL, NULL, mach64_write, NULL, NULL, mach64); - mem_removehandler(0xa0000, 0x20000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); - mem_removehandler(0xbc000, 0x04000, mach64_ext_readb, mach64_ext_readw, mach64_ext_readl, mach64_ext_writeb, mach64_ext_writew, mach64_ext_writel, mach64); - if (mach64->old_linear_base >= (mem_size << 20)) - { - mem_removehandler(mach64->old_linear_base, (8 << 20) - 0x4000, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, svga); - mem_removehandler(mach64->old_linear_base + ((8 << 20) - 0x4000), 0x4000, mach64_ext_readb, mach64_ext_readw, mach64_ext_readl, mach64_ext_writeb, mach64_ext_writew, mach64_ext_writel, mach64); - } + + mem_mapping_disable(&mach64->mmio_mapping); // pclog("Write mapping %02X\n", val); switch (svga->gdcreg[6] & 0xc) { case 0x0: /*128k at A0000*/ - mem_sethandler(0xa0000, 0x10000, mach64_read, NULL, NULL, mach64_write, NULL, NULL, mach64); - mem_sethandler(0xbc000, 0x04000, mach64_ext_readb, mach64_ext_readw, mach64_ext_readl, mach64_ext_writeb, mach64_ext_writew, mach64_ext_writel, mach64); + mem_mapping_set_handler(&mach64->svga.mapping, mach64_read, NULL, NULL, mach64_write, NULL, NULL); + mem_mapping_set_p(&mach64->svga.mapping, mach64); + mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000); + mem_mapping_enable(&mach64->mmio_mapping); break; case 0x4: /*64k at A0000*/ - mem_sethandler(0xa0000, 0x10000, mach64_read, NULL, NULL, mach64_write, NULL, NULL, mach64); + mem_mapping_set_handler(&mach64->svga.mapping, mach64_read, NULL, NULL, mach64_write, NULL, NULL); + mem_mapping_set_p(&mach64->svga.mapping, mach64); + mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000); break; case 0x8: /*32k at B0000*/ - mem_sethandler(0xb0000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); + mem_mapping_set_handler(&mach64->svga.mapping, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel); + mem_mapping_set_p(&mach64->svga.mapping, svga); + mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000); break; case 0xC: /*32k at B8000*/ - mem_sethandler(0xb8000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); + mem_mapping_set_handler(&mach64->svga.mapping, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel); + mem_mapping_set_p(&mach64->svga.mapping, svga); + mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000); break; } - if (mach64->linear_base >= (mem_size << 20)) + if (mach64->linear_base) { - mem_sethandler(mach64->linear_base, (8 << 20) - 0x4000, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, svga); - mem_sethandler(mach64->linear_base + ((8 << 20) - 0x4000), 0x4000, mach64_ext_readb, mach64_ext_readw, mach64_ext_readl, mach64_ext_writeb, mach64_ext_writew, mach64_ext_writel, mach64); -// pclog("Mach64 LFB %08X\n", mach64->linear_base); + mem_mapping_set_addr(&mach64->linear_mapping, mach64->linear_base, (8 << 20) - 0x4000); + mem_mapping_set_addr(&mach64->mmio_linear_mapping, mach64->linear_base + ((8 << 20) - 0x4000), 0x4000); + } + else + { + mem_mapping_disable(&mach64->linear_mapping); + mem_mapping_disable(&mach64->mmio_linear_mapping); } - mach64->old_linear_base = mach64->linear_base; } #define READ8(addr, var) switch ((addr) & 3) \ @@ -2019,6 +2028,11 @@ void *mach64gx_init() mach64_in, mach64_out, mach64_hwcursor_draw); + mem_mapping_add(&mach64->linear_mapping, 0, 0, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, &mach64->svga); + mem_mapping_add(&mach64->mmio_linear_mapping, 0, 0, mach64_ext_readb, mach64_ext_readw, mach64_ext_readl, mach64_ext_writeb, mach64_ext_writew, mach64_ext_writel, mach64); + mem_mapping_add(&mach64->mmio_mapping, 0xbc000, 0x04000, mach64_ext_readb, mach64_ext_readw, mach64_ext_readl, mach64_ext_writeb, mach64_ext_writew, mach64_ext_writel, mach64); + mem_mapping_disable(&mach64->mmio_mapping); + io_sethandler(0x03c0, 0x0020, mach64_in, NULL, NULL, mach64_out, NULL, NULL, mach64); for (c = 0; c < 8; c++) diff --git a/src/vid_cga.c b/src/vid_cga.c index c033bb5..fcc71a7 100644 --- a/src/vid_cga.c +++ b/src/vid_cga.c @@ -497,7 +497,7 @@ void *cga_standalone_init() q_filt[c] = 512.0 * sin((3.14 * (cga_tint + c * 4) / 16.0) - 33.0 / 180.0); } timer_add(cga_poll, &cga->vidtime, TIMER_ALWAYS_ENABLED, cga); - mem_sethandler(0xb8000, 0x08000, cga_read, NULL, NULL, cga_write, NULL, NULL, cga); + mem_mapping_add(&cga->mapping, 0xb8000, 0x08000, cga_read, NULL, NULL, cga_write, NULL, NULL, cga); io_sethandler(0x03d0, 0x0010, cga_in, NULL, NULL, cga_out, NULL, NULL, cga); return cga; } diff --git a/src/vid_cga.h b/src/vid_cga.h index b9a52f1..ef6481b 100644 --- a/src/vid_cga.h +++ b/src/vid_cga.h @@ -1,5 +1,7 @@ typedef struct cga_t { + mem_mapping_t mapping; + int crtcreg; uint8_t crtc[32]; diff --git a/src/vid_cl5429.c b/src/vid_cl5429.c index e164827..4972cae 100644 --- a/src/vid_cl5429.c +++ b/src/vid_cl5429.c @@ -12,6 +12,8 @@ typedef struct gd5429_t { + mem_mapping_t mmio_mapping; + svga_t svga; uint32_t bank[2]; @@ -220,25 +222,25 @@ void gd5429_recalc_mapping(gd5429_t *gd5429) { svga_t *svga = &gd5429->svga; - mem_removehandler(0xa0000, 0x20000, gd5429_read, NULL, NULL, gd5429_write, NULL, NULL, gd5429); - mem_removehandler(0xa0000, 0x20000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); - mem_removehandler(0xb8000, 0x00100, gd5429_mmio_read, NULL, NULL, gd5429_mmio_write, NULL, NULL, gd5429); pclog("Write mapping %02X %i\n", svga->gdcreg[6], svga->seqregs[0x17] & 0x04); switch (svga->gdcreg[6] & 0x0C) { case 0x0: /*128k at A0000*/ - mem_sethandler(0xa0000, 0x10000, gd5429_read, NULL, NULL, gd5429_write, NULL, NULL, gd5429); + mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000); + mem_mapping_disable(&gd5429->mmio_mapping); break; case 0x4: /*64k at A0000*/ - mem_sethandler(0xa0000, 0x10000, gd5429_read, NULL, NULL, gd5429_write, NULL, NULL, gd5429); + mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000); if (svga->seqregs[0x17] & 0x04) - mem_sethandler(0xb8000, 0x00100, gd5429_mmio_read, NULL, NULL, gd5429_mmio_write, NULL, NULL, gd5429); + mem_mapping_set_addr(&gd5429->mmio_mapping, 0xb8000, 0x00100); break; case 0x8: /*32k at B0000*/ - mem_sethandler(0xb0000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); + mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000); + mem_mapping_disable(&gd5429->mmio_mapping); break; case 0xC: /*32k at B8000*/ - mem_sethandler(0xb8000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); + mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000); + mem_mapping_disable(&gd5429->mmio_mapping); break; } } @@ -539,13 +541,14 @@ void gd5429_start_blit(uint32_t cpu_dat, int count, void *p) if (gd5429->blt.mode & 0x04) { // pclog("blt.mode & 0x04\n"); - mem_removehandler(0xa0000, 0x10000, gd5429_read, NULL, NULL, gd5429_write, NULL, NULL, gd5429); - mem_sethandler(0xa0000, 0x10000, NULL, NULL, NULL, NULL, gd5429_blt_write_w, gd5429_blt_write_l, gd5429); + mem_mapping_set_handler(&svga->mapping, NULL, NULL, NULL, NULL, gd5429_blt_write_w, gd5429_blt_write_l); + mem_mapping_set_p(&svga->mapping, gd5429); return; } else { - mem_removehandler(0xa0000, 0x10000, NULL, NULL, NULL, NULL, gd5429_blt_write_w, gd5429_blt_write_l, gd5429); + mem_mapping_set_handler(&gd5429->svga.mapping, gd5429_read, NULL, NULL, gd5429_write, NULL, NULL); + mem_mapping_set_p(&gd5429->svga.mapping, gd5429); gd5429_recalc_mapping(gd5429); } } @@ -666,7 +669,8 @@ void gd5429_start_blit(uint32_t cpu_dat, int count, void *p) { if (gd5429->blt.mode & 0x04) { - mem_removehandler(0xa0000, 0x10000, NULL, NULL, NULL, NULL, gd5429_blt_write_w, gd5429_blt_write_l, gd5429); + mem_mapping_set_handler(&gd5429->svga.mapping, gd5429_read, NULL, NULL, gd5429_write, NULL, NULL); + mem_mapping_set_p(&gd5429->svga.mapping, gd5429); gd5429_recalc_mapping(gd5429); } return; @@ -808,6 +812,11 @@ void *gd5429_init() gd5429_in, gd5429_out, gd5429_hwcursor_draw); + mem_mapping_set_handler(&gd5429->svga.mapping, gd5429_read, NULL, NULL, gd5429_write, NULL, NULL); + mem_mapping_set_p(&gd5429->svga.mapping, gd5429); + + mem_mapping_add(&gd5429->mmio_mapping, 0, 0, gd5429_mmio_read, NULL, NULL, gd5429_mmio_write, NULL, NULL, gd5429); + io_sethandler(0x03c0, 0x0020, gd5429_in, NULL, NULL, gd5429_out, NULL, NULL, gd5429); svga->hwcursor.yoff = 32; diff --git a/src/vid_ega.c b/src/vid_ega.c index 06a67e4..c918e14 100644 --- a/src/vid_ega.c +++ b/src/vid_ega.c @@ -96,21 +96,20 @@ void ega_out(uint16_t addr, uint8_t val, void *p) ega->readmode = val & 8; break; case 6: - mem_removehandler(0xa0000, 0x20000, ega_read, NULL, NULL, ega_write, NULL, NULL, ega); // pclog("Write mapping %02X\n", val); switch (val & 0xc) { case 0x0: /*128k at A0000*/ - mem_sethandler(0xa0000, 0x20000, ega_read, NULL, NULL, ega_write, NULL, NULL, ega); + mem_mapping_set_addr(&ega->mapping, 0xa0000, 0x20000); break; case 0x4: /*64k at A0000*/ - mem_sethandler(0xa0000, 0x10000, ega_read, NULL, NULL, ega_write, NULL, NULL, ega); + mem_mapping_set_addr(&ega->mapping, 0xa0000, 0x10000); break; case 0x8: /*32k at B0000*/ - mem_sethandler(0xb0000, 0x08000, ega_read, NULL, NULL, ega_write, NULL, NULL, ega); + mem_mapping_set_addr(&ega->mapping, 0xb0000, 0x08000); break; case 0xC: /*32k at B8000*/ - mem_sethandler(0xb8000, 0x08000, ega_read, NULL, NULL, ega_write, NULL, NULL, ega); + mem_mapping_set_addr(&ega->mapping, 0xb8000, 0x08000); break; } break; @@ -814,6 +813,7 @@ void *ega_standalone_init() ega_init(ega); + mem_mapping_add(&ega->mapping, 0xa0000, 0x20000, ega_read, NULL, NULL, ega_write, NULL, NULL, ega); timer_add(ega_poll, &ega->vidtime, TIMER_ALWAYS_ENABLED, ega); io_sethandler(0x03a0, 0x0040, ega_in, NULL, NULL, ega_out, NULL, NULL, ega); return ega; diff --git a/src/vid_ega.h b/src/vid_ega.h index c90a19f..f8039c5 100644 --- a/src/vid_ega.h +++ b/src/vid_ega.h @@ -1,5 +1,7 @@ typedef struct ega_t { + mem_mapping_t mapping; + uint8_t crtcreg; uint8_t crtc[32]; uint8_t gdcreg[16]; diff --git a/src/vid_et4000.c b/src/vid_et4000.c index f449747..697a4a0 100644 --- a/src/vid_et4000.c +++ b/src/vid_et4000.c @@ -3,6 +3,7 @@ #include "ibm.h" #include "device.h" #include "io.h" +#include "mem.h" #include "video.h" #include "vid_svga.h" #include "vid_unk_ramdac.h" diff --git a/src/vid_et4000w32.c b/src/vid_et4000w32.c index 2ae15d5..0d80eb2 100644 --- a/src/vid_et4000w32.c +++ b/src/vid_et4000w32.c @@ -7,15 +7,18 @@ #include "ibm.h" #include "device.h" #include "io.h" +#include "mem.h" #include "pci.h" #include "video.h" #include "vid_svga.h" #include "vid_icd2061.h" #include "vid_stg_ramdac.h" -#include "mem.h" typedef struct et4000w32p_t { + mem_mapping_t linear_mapping; + mem_mapping_t mmu_mapping; + svga_t svga; stg_ramdac_t ramdac; icd2061_t icd2061; @@ -258,12 +261,11 @@ void et4000w32p_recalcmapping(et4000w32p_t *et4000) svga_t *svga = &et4000->svga; pclog("recalcmapping %p\n", svga); - mem_removehandler(et4000->linearbase_old, 0x200000, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, svga); - mem_removehandler( 0xa0000, 0x20000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); - mem_removehandler( 0xb0000, 0x10000, et4000w32p_mmu_read, NULL, NULL, et4000w32p_mmu_write, NULL, NULL, et4000); if (svga->crtc[0x36] & 0x10) /*Linear frame buffer*/ { - mem_sethandler(et4000->linearbase, 0x200000, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, svga); + mem_mapping_set_addr(&et4000->linear_mapping, et4000->linearbase, 0x200000); + mem_mapping_disable(&svga->mapping); + mem_mapping_disable(&et4000->mmu_mapping); } else { @@ -273,30 +275,36 @@ void et4000w32p_recalcmapping(et4000w32p_t *et4000) switch (map) { case 0x0: case 0x4: case 0x8: case 0xC: /*128k at A0000*/ - mem_sethandler(0xa0000, 0x20000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); + mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000); + mem_mapping_disable(&et4000->mmu_mapping); break; case 0x1: /*64k at A0000*/ - mem_sethandler(0xa0000, 0x10000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); + mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000); + mem_mapping_disable(&et4000->mmu_mapping); break; case 0x2: /*32k at B0000*/ - mem_sethandler(0xb0000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); + mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000); + mem_mapping_disable(&et4000->mmu_mapping); break; case 0x3: /*32k at B8000*/ - mem_sethandler(0xb8000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); + mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000); + mem_mapping_disable(&et4000->mmu_mapping); break; case 0x5: case 0x9: case 0xD: /*64k at A0000, MMU at B8000*/ - mem_sethandler(0xa0000, 0x10000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); - mem_sethandler(0xb8000, 0x08000, et4000w32p_mmu_read, NULL, NULL, et4000w32p_mmu_write, NULL, NULL, et4000); + mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000); + mem_mapping_set_addr(&et4000->mmu_mapping, 0xb8000, 0x08000); break; case 0x6: case 0xA: case 0xE: /*32k at B0000, MMU at A8000*/ - mem_sethandler(0xa8000, 0x08000, et4000w32p_mmu_read, NULL, NULL, et4000w32p_mmu_write, NULL, NULL, et4000); - mem_sethandler(0xb0000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); + mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000); + mem_mapping_set_addr(&et4000->mmu_mapping, 0xa8000, 0x08000); break; case 0x7: case 0xB: case 0xF: /*32k at B8000, MMU at A8000*/ - mem_sethandler(0xa8000, 0x08000, et4000w32p_mmu_read, NULL, NULL, et4000w32p_mmu_write, NULL, NULL, et4000); - mem_sethandler(0xb8000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); + mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000); + mem_mapping_set_addr(&et4000->mmu_mapping, 0xa8000, 0x08000); break; } + + mem_mapping_disable(&et4000->linear_mapping); // pclog("ET4K map %02X\n", map); } et4000->linearbase_old = et4000->linearbase; @@ -933,6 +941,9 @@ void *et4000w32p_init() et4000w32p_in, et4000w32p_out, et4000w32p_hwcursor_draw); + mem_mapping_add(&et4000->linear_mapping, 0, 0, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, &et4000->svga); + mem_mapping_add(&et4000->mmu_mapping, 0, 0, et4000w32p_mmu_read, NULL, NULL, et4000w32p_mmu_write, NULL, NULL, et4000); + io_sethandler(0x03c0, 0x0020, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000); io_sethandler(0x210A, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000); diff --git a/src/vid_hercules.c b/src/vid_hercules.c index 534feee..e9ac6aa 100644 --- a/src/vid_hercules.c +++ b/src/vid_hercules.c @@ -9,6 +9,8 @@ typedef struct hercules_t { + mem_mapping_t mapping; + uint8_t crtc[32]; int crtcreg; @@ -59,9 +61,10 @@ void hercules_out(uint16_t addr, uint8_t val, void *p) return; case 0x3bf: hercules->ctrl2 = val; - mem_removehandler(0xb8000, 0x08000, hercules_read, NULL, NULL, hercules_write, NULL, NULL, hercules); if (val & 2) - mem_sethandler(0xb8000, 0x08000, hercules_read, NULL, NULL, hercules_write, NULL, NULL, hercules); + mem_mapping_set_addr(&hercules->mapping, 0xb0000, 0x10000); + else + mem_mapping_set_addr(&hercules->mapping, 0xb0000, 0x08000); return; } } @@ -308,7 +311,7 @@ void *hercules_init() hercules->vram = malloc(0x10000); timer_add(hercules_poll, &hercules->vidtime, TIMER_ALWAYS_ENABLED, hercules); - mem_sethandler(0xb0000, 0x08000, hercules_read, NULL, NULL, hercules_write, NULL, NULL, hercules); + mem_mapping_add(&hercules->mapping, 0xb0000, 0x08000, hercules_read, NULL, NULL, hercules_write, NULL, NULL, hercules); io_sethandler(0x03b0, 0x0010, hercules_in, NULL, NULL, hercules_out, NULL, NULL, hercules); for (c = 0; c < 256; c++) diff --git a/src/vid_mda.c b/src/vid_mda.c index 944c891..4eea5c2 100644 --- a/src/vid_mda.c +++ b/src/vid_mda.c @@ -10,6 +10,8 @@ typedef struct mda_t { + mem_mapping_t mapping; + uint8_t crtc[32]; int crtcreg; @@ -266,7 +268,7 @@ void *mda_init() mda->vram = malloc(0x1000); timer_add(mda_poll, &mda->vidtime, TIMER_ALWAYS_ENABLED, mda); - mem_sethandler(0xb0000, 0x08000, mda_read, NULL, NULL, mda_write, NULL, NULL, mda); + mem_mapping_add(&mda->mapping, 0xb0000, 0x08000, mda_read, NULL, NULL, mda_write, NULL, NULL, mda); io_sethandler(0x03b0, 0x0010, mda_in, NULL, NULL, mda_out, NULL, NULL, mda); for (c = 0; c < 256; c++) diff --git a/src/vid_olivetti_m24.c b/src/vid_olivetti_m24.c index ee9a5ce..3c3eea5 100644 --- a/src/vid_olivetti_m24.c +++ b/src/vid_olivetti_m24.c @@ -11,6 +11,8 @@ typedef struct m24_t { + mem_mapping_t mapping; + uint8_t crtc[32]; int crtcreg; @@ -457,7 +459,7 @@ void *m24_init() m24->vram = malloc(0x8000); timer_add(m24_poll, &m24->vidtime, TIMER_ALWAYS_ENABLED, m24); - mem_sethandler(0xb8000, 0x08000, m24_read, NULL, NULL, m24_write, NULL, NULL, m24); + mem_mapping_add(&m24->mapping, 0xb8000, 0x08000, m24_read, NULL, NULL, m24_write, NULL, NULL, m24); io_sethandler(0x03d0, 0x0010, m24_in, NULL, NULL, m24_out, NULL, NULL, m24); return m24; } diff --git a/src/vid_oti067.c b/src/vid_oti067.c index 74dc7e0..343b8b6 100644 --- a/src/vid_oti067.c +++ b/src/vid_oti067.c @@ -3,6 +3,7 @@ #include "ibm.h" #include "device.h" #include "io.h" +#include "mem.h" #include "video.h" #include "vid_oti067.h" #include "vid_svga.h" diff --git a/src/vid_paradise.c b/src/vid_paradise.c index b2f7902..adc26b8 100644 --- a/src/vid_paradise.c +++ b/src/vid_paradise.c @@ -65,21 +65,20 @@ void paradise_out(uint16_t addr, uint8_t val, void *p) { if ((svga->gdcreg[6] & 0xc) != (val & 0xc)) { - mem_removehandler(0xa0000, 0x20000, paradise_read, NULL, NULL, paradise_write, NULL, NULL, paradise); // pclog("Write mapping %02X\n", val); switch (val&0xC) { case 0x0: /*128k at A0000*/ - mem_sethandler(0xa0000, 0x20000, paradise_read, NULL, NULL, paradise_write, NULL, NULL, paradise); + mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000); break; case 0x4: /*64k at A0000*/ - mem_sethandler(0xa0000, 0x10000, paradise_read, NULL, NULL, paradise_write, NULL, NULL, paradise); + mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000); break; case 0x8: /*32k at B0000*/ - mem_sethandler(0xb0000, 0x08000, paradise_read, NULL, NULL, paradise_write, NULL, NULL, paradise); + mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000); break; case 0xC: /*32k at B8000*/ - mem_sethandler(0xb8000, 0x08000, paradise_read, NULL, NULL, paradise_write, NULL, NULL, paradise); + mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000); break; } } @@ -260,6 +259,9 @@ void *paradise_pvga1a_init() paradise_in, paradise_out, NULL); + mem_mapping_set_handler(¶dise->svga.mapping, paradise_read, NULL, NULL, paradise_write, NULL, NULL); + mem_mapping_set_p(¶dise->svga.mapping, paradise); + svga->crtc[0x31] = 'W'; svga->crtc[0x32] = 'D'; svga->crtc[0x33] = '9'; @@ -287,6 +289,9 @@ void *paradise_wd90c11_init() paradise_in, paradise_out, NULL); + mem_mapping_set_handler(¶dise->svga.mapping, paradise_read, NULL, NULL, paradise_write, NULL, NULL); + mem_mapping_set_p(¶dise->svga.mapping, paradise); + svga->crtc[0x31] = 'W'; svga->crtc[0x32] = 'D'; svga->crtc[0x33] = '9'; diff --git a/src/vid_pc1512.c b/src/vid_pc1512.c index 6085ca1..175ef00 100644 --- a/src/vid_pc1512.c +++ b/src/vid_pc1512.c @@ -17,6 +17,8 @@ typedef struct pc1512_t { + mem_mapping_t mapping; + uint8_t crtc[32]; int crtcreg; @@ -456,7 +458,7 @@ static void *pc1512_init() pc1512->cgamode = 0x12; timer_add(pc1512_poll, &pc1512->vidtime, TIMER_ALWAYS_ENABLED, pc1512); - mem_sethandler(0xb8000, 0x08000, pc1512_read, NULL, NULL, pc1512_write, NULL, NULL, pc1512); + mem_mapping_add(&pc1512->mapping, 0xb8000, 0x08000, pc1512_read, NULL, NULL, pc1512_write, NULL, NULL, pc1512); io_sethandler(0x03d0, 0x0010, pc1512_in, NULL, NULL, pc1512_out, NULL, NULL, pc1512); return pc1512; } diff --git a/src/vid_pc1640.c b/src/vid_pc1640.c index 3f84f31..48463e4 100644 --- a/src/vid_pc1640.c +++ b/src/vid_pc1640.c @@ -13,6 +13,9 @@ typedef struct pc1640_t { + mem_mapping_t cga_mapping; + mem_mapping_t ega_mapping; + cga_t cga; ega_t ega; @@ -28,25 +31,27 @@ void pc1640_out(uint16_t addr, uint8_t val, void *p) { case 0x3db: pc1640->cga_enabled = val & 0x40; - mem_removehandler(0xa0000, 0x20000, ega_read, NULL, NULL, ega_write, NULL, NULL, &pc1640->ega); - mem_removehandler(0xb8000, 0x08000, cga_read, NULL, NULL, cga_write, NULL, NULL, &pc1640->cga); if (pc1640->cga_enabled) - mem_sethandler(0xb8000, 0x08000, cga_read, NULL, NULL, cga_write, NULL, NULL, &pc1640->cga); + { + mem_mapping_enable(&pc1640->cga_mapping); + mem_mapping_disable(&pc1640->ega_mapping); + } else - { + { + mem_mapping_disable(&pc1640->cga_mapping); switch (pc1640->ega.gdcreg[6] & 0xc) { case 0x0: /*128k at A0000*/ - mem_sethandler(0xa0000, 0x20000, ega_read, NULL, NULL, ega_write, NULL, NULL, &pc1640->ega); + mem_mapping_set_addr(&pc1640->ega_mapping, 0xa0000, 0x20000); break; case 0x4: /*64k at A0000*/ - mem_sethandler(0xa0000, 0x10000, ega_read, NULL, NULL, ega_write, NULL, NULL, &pc1640->ega); + mem_mapping_set_addr(&pc1640->ega_mapping, 0xa0000, 0x10000); break; case 0x8: /*32k at B0000*/ - mem_sethandler(0xb0000, 0x08000, ega_read, NULL, NULL, ega_write, NULL, NULL, &pc1640->ega); + mem_mapping_set_addr(&pc1640->ega_mapping, 0xb0000, 0x08000); break; case 0xC: /*32k at B8000*/ - mem_sethandler(0xb8000, 0x08000, ega_read, NULL, NULL, ega_write, NULL, NULL, &pc1640->ega); + mem_mapping_set_addr(&pc1640->ega_mapping, 0xb8000, 0x08000); break; } } @@ -115,7 +120,8 @@ void *pc1640_init() cga_init(&pc1640->cga); timer_add(pc1640_poll, &pc1640->vidtime, TIMER_ALWAYS_ENABLED, pc1640); - mem_sethandler(0xb8000, 0x08000, cga_read, NULL, NULL, cga_write, NULL, NULL, cga); + mem_mapping_add(&pc1640->cga_mapping, 0xb8000, 0x08000, cga_read, NULL, NULL, cga_write, NULL, NULL, cga); + mem_mapping_add(&pc1640->ega_mapping, 0, 0, ega_read, NULL, NULL, ega_write, NULL, NULL, ega); io_sethandler(0x03a0, 0x0040, pc1640_in, NULL, NULL, pc1640_out, NULL, NULL, pc1640); return cga; } diff --git a/src/vid_pc200.c b/src/vid_pc200.c index 62f5128..f461f6b 100644 --- a/src/vid_pc200.c +++ b/src/vid_pc200.c @@ -13,6 +13,8 @@ typedef struct pc200_t { + mem_mapping_t mapping; + cga_t cga; uint8_t reg_3dd, reg_3de, reg_3df; @@ -109,7 +111,7 @@ void *pc200_init() cga_init(&pc200->cga); timer_add(cga_poll, &cga->vidtime, TIMER_ALWAYS_ENABLED, cga); - mem_sethandler(0xb8000, 0x08000, cga_read, NULL, NULL, cga_write, NULL, NULL, cga); + mem_mapping_add(&pc200->mapping, 0xb8000, 0x08000, cga_read, NULL, NULL, cga_write, NULL, NULL, cga); io_sethandler(0x03d0, 0x0010, pc200_in, NULL, NULL, pc200_out, NULL, NULL, pc200); return cga; } diff --git a/src/vid_s3.c b/src/vid_s3.c index 40ca424..4a6531a 100644 --- a/src/vid_s3.c +++ b/src/vid_s3.c @@ -13,6 +13,9 @@ typedef struct s3_t { + mem_mapping_t linear_mapping; + mem_mapping_t mmio_mapping; + svga_t svga; sdac_ramdac_t ramdac; @@ -239,7 +242,7 @@ void s3_recalctimings(svga_t *svga) s3_t *s3 = (s3_t *)svga->p; svga->hdisp = svga->hdisp_old; - pclog("%i %i\n", svga->hdisp, svga->hdisp_time); +// pclog("%i %i\n", svga->hdisp, svga->hdisp_time); // pclog("recalctimings\n"); svga->ma_latch |= (s3->ma_ext << 16); // pclog("SVGA_MA %08X\n", svga_ma); @@ -287,41 +290,38 @@ void s3_recalctimings(svga_t *svga) } // if (svga->bpp == 32) svga->hdisp *= 3; - pclog("svga->hdisp %i %02X %i\n", svga->hdisp, svga->crtc[0x5d], svga->hdisp_time); +// pclog("svga->hdisp %i %02X %i\n", svga->hdisp, svga->crtc[0x5d], svga->hdisp_time); } void s3_updatemapping(s3_t *s3) { svga_t *svga = &s3->svga; - mem_removehandler(s3->linear_base, s3->linear_size, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, svga); - // video_write_a000_w = video_write_a000_l = NULL; - mem_removehandler(0xa0000, 0x20000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); - mem_removehandler(0xa0000, 0x10000, s3_accel_read, NULL, NULL, s3_accel_write, s3_accel_write_w, s3_accel_write_l, s3); - -// pclog("Update mapping - bank %02X ", gdcreg[6] & 0xc); +// pclog("Update mapping - bank %02X ", svga->gdcreg[6] & 0xc); switch (svga->gdcreg[6] & 0xc) /*Banked framebuffer*/ { case 0x0: /*128k at A0000*/ - mem_sethandler(0xa0000, 0x20000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); + mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000); break; case 0x4: /*64k at A0000*/ - mem_sethandler(0xa0000, 0x10000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); + mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000); break; case 0x8: /*32k at B0000*/ - mem_sethandler(0xb0000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); + mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000); break; case 0xC: /*32k at B8000*/ - mem_sethandler(0xb8000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); + mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000); break; } -// pclog("Linear framebuffer %02X ", crtc[0x58] & 0x10); +// pclog("Linear framebuffer %02X ", svga->crtc[0x58] & 0x10); if (svga->crtc[0x58] & 0x10) /*Linear framebuffer*/ { + mem_mapping_disable(&svga->mapping); + s3->linear_base = (svga->crtc[0x5a] << 16) | (svga->crtc[0x59] << 24); switch (svga->crtc[0x58] & 3) { @@ -340,16 +340,24 @@ void s3_updatemapping(s3_t *s3) } s3->linear_base &= ~(s3->linear_size - 1); // pclog("%08X %08X %02X %02X %02X\n", linear_base, linear_size, crtc[0x58], crtc[0x59], crtc[0x5a]); -// pclog("Linear framebuffer at %08X size %08X\n", linear_base, linear_size); +// pclog("Linear framebuffer at %08X size %08X\n", s3->linear_base, s3->linear_size); if (s3->linear_base == 0xa0000) - mem_sethandler(0xa0000, 0x10000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); + { + mem_mapping_disable(&s3->linear_mapping); + mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000); +// mem_mapping_set_addr(&s3->linear_mapping, 0xa0000, 0x10000); + } else - mem_sethandler(s3->linear_base, s3->linear_size, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, svga); + mem_mapping_set_addr(&s3->linear_mapping, s3->linear_base, s3->linear_size); } + else + mem_mapping_disable(&s3->linear_mapping); -// pclog("Memory mapped IO %02X\n", crtc[0x53] & 0x10); +// pclog("Memory mapped IO %02X\n", svga->crtc[0x53] & 0x10); if (svga->crtc[0x53] & 0x10) /*Memory mapped IO*/ - mem_sethandler(0xa0000, 0x10000, s3_accel_read, NULL, NULL, s3_accel_write, s3_accel_write_w, s3_accel_write_l, s3); + mem_mapping_enable(&s3->mmio_mapping); + else + mem_mapping_disable(&s3->mmio_mapping); } @@ -1533,6 +1541,10 @@ static void *s3_init() svga_t *svga = &s3->svga; memset(s3, 0, sizeof(s3_t)); + mem_mapping_add(&s3->linear_mapping, 0, 0, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, &s3->svga); + mem_mapping_add(&s3->mmio_mapping, 0xa0000, 0x10000, s3_accel_read, NULL, NULL, s3_accel_write, s3_accel_write_w, s3_accel_write_l, s3); + mem_mapping_disable(&s3->mmio_mapping); + svga_init(&s3->svga, s3, 1 << 22, /*4mb - 864 supports 8mb but buggy VESA driver reports 0mb*/ s3_recalctimings, s3_in, s3_out, diff --git a/src/vid_s3_virge.c b/src/vid_s3_virge.c index adc4998..0a0ca99 100644 --- a/src/vid_s3_virge.c +++ b/src/vid_s3_virge.c @@ -15,6 +15,9 @@ typedef struct virge_t { + mem_mapping_t linear_mapping; + mem_mapping_t mmio_mapping; + svga_t svga; uint8_t bank; @@ -263,26 +266,20 @@ void s3_virge_updatemapping(virge_t *virge) { svga_t *svga = &virge->svga; - mem_removehandler(virge->linear_base, virge->linear_size, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, svga); - -// video_write_a000_w = video_write_a000_l = NULL; - - mem_removehandler(0xa0000, 0x20000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); - mem_removehandler(0xa0000, 0x20000, s3_virge_mmio_read, s3_virge_mmio_read_w, s3_virge_mmio_read_l, s3_virge_mmio_write, s3_virge_mmio_write_w, s3_virge_mmio_write_l, virge); pclog("Update mapping - bank %02X ", svga->gdcreg[6] & 0xc); switch (svga->gdcreg[6] & 0xc) /*Banked framebuffer*/ { case 0x0: /*128k at A0000*/ - mem_sethandler(0xa0000, 0x20000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); + mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000); break; case 0x4: /*64k at A0000*/ - mem_sethandler(0xa0000, 0x10000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); + mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000); break; case 0x8: /*32k at B0000*/ - mem_sethandler(0xb0000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); + mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000); break; case 0xC: /*32k at B8000*/ - mem_sethandler(0xb8000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); + mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000); break; } @@ -309,20 +306,26 @@ void s3_virge_updatemapping(virge_t *virge) // pclog("%08X %08X %02X %02X %02X\n", linear_base, linear_size, crtc[0x58], crtc[0x59], crtc[0x5a]); pclog("Linear framebuffer at %08X size %08X\n", virge->linear_base, virge->linear_size); if (virge->linear_base == 0xa0000) - mem_sethandler(0xa0000, 0x10000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); + { + mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000); + mem_mapping_disable(&virge->linear_mapping); + } else - mem_sethandler(virge->linear_base, virge->linear_size, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, svga); + mem_mapping_set_addr(&svga->mapping, virge->linear_base, virge->linear_size); } + else + mem_mapping_disable(&virge->linear_mapping); pclog("Memory mapped IO %02X\n", svga->crtc[0x53] & 0x18); if ((svga->crtc[0x53] & 0x18) == 0x10) /*Memory mapped IO*/ { if (svga->crtc[0x53] & 0x20) - mem_sethandler(0xb8000, 0x8000, s3_virge_mmio_read, s3_virge_mmio_read_w, s3_virge_mmio_read_l, s3_virge_mmio_write, s3_virge_mmio_write_w, s3_virge_mmio_write_l, virge); + mem_mapping_set_addr(&virge->mmio_mapping, 0xb8000, 0x8000); else - mem_sethandler(0xa8000, 0x8000, s3_virge_mmio_read, s3_virge_mmio_read_w, s3_virge_mmio_read_l, s3_virge_mmio_write, s3_virge_mmio_write_w, s3_virge_mmio_write_l, virge); + mem_mapping_set_addr(&virge->mmio_mapping, 0xa8000, 0x8000); } - + else + mem_mapping_disable(&virge->mmio_mapping); } @@ -451,6 +454,9 @@ void *s3_virge_init() s3_virge_in, s3_virge_out, s3_virge_hwcursor_draw); + mem_mapping_add(&virge->mmio_mapping, 0, 0, s3_virge_mmio_read, s3_virge_mmio_read_w, s3_virge_mmio_read_l, s3_virge_mmio_write, s3_virge_mmio_write_w, s3_virge_mmio_write_l, virge); + mem_mapping_add(&virge->linear_mapping, 0, 0, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, &virge->svga); + io_sethandler(0x03c0, 0x0020, s3_virge_in, NULL, NULL, s3_virge_out, NULL, NULL, virge); virge->pci_regs[4] = 3; diff --git a/src/vid_sdac_ramdac.c b/src/vid_sdac_ramdac.c index 2ccbb36..196c70a 100644 --- a/src/vid_sdac_ramdac.c +++ b/src/vid_sdac_ramdac.c @@ -1,6 +1,7 @@ /*87C716 'SDAC' true colour RAMDAC emulation*/ /*Misidentifies as AT&T 21C504*/ #include "ibm.h" +#include "mem.h" #include "video.h" #include "vid_svga.h" #include "vid_sdac_ramdac.h" diff --git a/src/vid_stg_ramdac.c b/src/vid_stg_ramdac.c index 82bbf07..2afcee8 100644 --- a/src/vid_stg_ramdac.c +++ b/src/vid_stg_ramdac.c @@ -1,5 +1,6 @@ /*STG1702 true colour RAMDAC emulation*/ #include "ibm.h" +#include "mem.h" #include "video.h" #include "vid_svga.h" #include "vid_stg_ramdac.h" diff --git a/src/vid_svga.c b/src/vid_svga.c index a267c1a..739cbfe 100644 --- a/src/vid_svga.c +++ b/src/vid_svga.c @@ -139,21 +139,20 @@ void svga_out(uint16_t addr, uint8_t val, void *p) pclog("svga_out recalcmapping %p\n", svga); if ((svga->gdcreg[6] & 0xc) != (val & 0xc)) { - mem_removehandler(0xa0000, 0x20000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, p); pclog("Write mapping %02X\n", val); switch (val&0xC) { case 0x0: /*128k at A0000*/ - mem_sethandler(0xa0000, 0x20000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, p); + mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000); break; case 0x4: /*64k at A0000*/ - mem_sethandler(0xa0000, 0x10000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, p); + mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000); break; case 0x8: /*32k at B0000*/ - mem_sethandler(0xb0000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, p); + mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000); break; case 0xC: /*32k at B8000*/ - mem_sethandler(0xb8000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, p); + mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000); break; } } @@ -641,7 +640,9 @@ int svga_init(svga_t *svga, void *p, int memsize, svga->video_out = video_out; svga->hwcursor_draw = hwcursor_draw; // _svga_recalctimings(svga); - + + mem_mapping_add(&svga->mapping, 0xa0000, 0x20000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); + timer_add(svga_poll, &svga->vidtime, TIMER_ALWAYS_ENABLED, svga); vramp = svga->vram; return 0; @@ -1161,7 +1162,7 @@ void svga_writew(uint32_t addr, uint16_t val, void *p) cycles -= video_timing_w; cycles_lost += video_timing_w; - if (svga_output) pclog("Writew %05X ", addr); + if (svga_output) pclog("svga_writew: %05X ", addr); addr = (addr & 0xffff) + svga->write_bank; addr &= 0x7FFFFF; if (addr >= svga->vram_limit) @@ -1189,7 +1190,7 @@ void svga_writel(uint32_t addr, uint32_t val, void *p) cycles -= video_timing_l; cycles_lost += video_timing_l; - if (svga_output) pclog("Writel %05X ", addr); + if (svga_output) pclog("svga_writel: %05X ", addr); addr = (addr & 0xffff) + svga->write_bank; addr &= 0x7FFFFF; if (addr >= svga->vram_limit) diff --git a/src/vid_svga.h b/src/vid_svga.h index b1c4f65..30a79e9 100644 --- a/src/vid_svga.h +++ b/src/vid_svga.h @@ -1,5 +1,7 @@ typedef struct svga_t { + mem_mapping_t mapping; + uint8_t crtcreg; uint8_t crtc[128]; uint8_t gdcreg[16]; diff --git a/src/vid_svga_render.c b/src/vid_svga_render.c index 3cc0fe3..d0b76d0 100644 --- a/src/vid_svga_render.c +++ b/src/vid_svga_render.c @@ -1,4 +1,5 @@ #include "ibm.h" +#include "mem.h" #include "video.h" #include "vid_svga.h" #include "vid_svga_render.h" diff --git a/src/vid_tandy.c b/src/vid_tandy.c index 264edbf..0d5f5d1 100644 --- a/src/vid_tandy.c +++ b/src/vid_tandy.c @@ -12,6 +12,8 @@ static int i_filt[8],q_filt[8]; typedef struct tandy_t { + mem_mapping_t mapping; + uint8_t crtc[32]; int crtcreg; @@ -665,7 +667,7 @@ void *tandy_init() q_filt[c] = 512.0 * sin((3.14 * (tandy_tint + c * 4) / 16.0) - 33.0 / 180.0); } timer_add(tandy_poll, &tandy->vidtime, TIMER_ALWAYS_ENABLED, tandy); - mem_sethandler(0xb8000, 0x08000, tandy_read, NULL, NULL, tandy_write, NULL, NULL, tandy); + mem_mapping_add(&tandy->mapping, 0xb8000, 0x08000, tandy_read, NULL, NULL, tandy_write, NULL, NULL, tandy); io_sethandler(0x03d0, 0x0010, tandy_in, NULL, NULL, tandy_out, NULL, NULL, tandy); io_sethandler(0x00a0, 0x0001, tandy_in, NULL, NULL, tandy_out, NULL, NULL, tandy); return tandy; diff --git a/src/vid_tkd8001_ramdac.c b/src/vid_tkd8001_ramdac.c index 4eb6bc6..d47df85 100644 --- a/src/vid_tkd8001_ramdac.c +++ b/src/vid_tkd8001_ramdac.c @@ -1,5 +1,6 @@ /*Trident TKD8001 RAMDAC emulation*/ #include "ibm.h" +#include "mem.h" #include "video.h" #include "vid_svga.h" #include "vid_tkd8001_ramdac.h" diff --git a/src/vid_tvga.c b/src/vid_tvga.c index b29d431..378b9e6 100644 --- a/src/vid_tvga.c +++ b/src/vid_tvga.c @@ -12,6 +12,9 @@ typedef struct tvga_t { + mem_mapping_t linear_mapping; + mem_mapping_t accel_mapping; + svga_t svga; tkd8001_ramdac_t ramdac; @@ -314,37 +317,37 @@ void tvga_recalcmapping(tvga_t *tvga) { svga_t *svga = &tvga->svga; - pclog("tvga_recalcmapping : %02X %02X\n", svga->crtc[0x21], svga->gdcreg[6]); - mem_removehandler(0xa0000, 0x20000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); - mem_removehandler(tvga->linear_base, tvga->linear_size, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, svga); - mem_removehandler(0xbc000, 0x4000, tvga_accel_read, NULL, NULL, tvga_accel_write, NULL, NULL, tvga); +// pclog("tvga_recalcmapping : %02X %02X\n", svga->crtc[0x21], svga->gdcreg[6]); if (svga->crtc[0x21] & 0x20) { + mem_mapping_disable(&svga->mapping); tvga->linear_base = ((svga->crtc[0x21] & 0xf) | ((svga->crtc[0x21] >> 2) & 0x30)) << 20; tvga->linear_size = (svga->crtc[0x21] & 0x10) ? 0x200000 : 0x100000; - mem_sethandler(tvga->linear_base, tvga->linear_size, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, svga); - pclog("Trident linear framebuffer at %08X - size %06X\n", tvga->linear_base, tvga->linear_size); - mem_sethandler(0xbc000, 0x4000, tvga_accel_read, tvga_accel_read_w, tvga_accel_read_l, tvga_accel_write, tvga_accel_write_w, tvga_accel_write_l, tvga); + mem_mapping_set_addr(&tvga->linear_mapping, tvga->linear_base, tvga->linear_size); +// pclog("Trident linear framebuffer at %08X - size %06X\n", tvga->linear_base, tvga->linear_size); + mem_mapping_enable(&tvga->accel_mapping); } else { // pclog("Write mapping %02X\n", val); + mem_mapping_disable(&tvga->linear_mapping); + mem_mapping_disable(&tvga->accel_mapping); switch (svga->gdcreg[6] & 0xC) { case 0x0: /*128k at A0000*/ - mem_sethandler(0xa0000, 0x20000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); + mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000); break; case 0x4: /*64k at A0000*/ - mem_sethandler(0xa0000, 0x10000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); - mem_sethandler(0xbc000, 0x4000, tvga_accel_read, NULL, NULL, tvga_accel_write, NULL, NULL, tvga); + mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000); + mem_mapping_enable(&tvga->accel_mapping); break; case 0x8: /*32k at B0000*/ - mem_sethandler(0xb0000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); + mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000); break; case 0xC: /*32k at B8000*/ - mem_sethandler(0xb8000, 0x08000, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel, svga); - break; + mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000); + break; } } } @@ -385,6 +388,11 @@ void *tvga8900d_init() tvga_in, tvga_out, NULL); + mem_mapping_add(&tvga->linear_mapping, 0, 0, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, &tvga->svga); + mem_mapping_add(&tvga->accel_mapping, 0xbc000, 0x4000, tvga_accel_read, tvga_accel_read_w, tvga_accel_read_l, tvga_accel_write, tvga_accel_write_w, tvga_accel_write_l, tvga); + mem_mapping_disable(&tvga->linear_mapping); + mem_mapping_disable(&tvga->accel_mapping); + io_sethandler(0x03c0, 0x0020, tvga_in, NULL, NULL, tvga_out, NULL, NULL, tvga); return tvga; @@ -399,6 +407,10 @@ void *tgui9440_init() tvga_in, tvga_out, tvga_hwcursor_draw); + mem_mapping_add(&tvga->linear_mapping, 0, 0, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, &tvga->svga); + mem_mapping_add(&tvga->accel_mapping, 0xbc000, 0x4000, tvga_accel_read, tvga_accel_read_w, tvga_accel_read_l, tvga_accel_write, tvga_accel_write_w, tvga_accel_write_l, tvga); + mem_mapping_disable(&tvga->accel_mapping); + io_sethandler(0x03c0, 0x0020, tvga_in, NULL, NULL, tvga_out, NULL, NULL, tvga); return tvga; @@ -549,15 +561,15 @@ void tvga_accel_command(int count, uint32_t cpu_dat, tvga_t *tvga) } } } - for (y = 0; y < 8; y++) +/* for (y = 0; y < 8; y++) { if (count == -1) pclog("Pattern %i : %02X %02X %02X %02X %02X %02X %02X %02X\n", y, tvga->accel.tvga_pattern[y][0], tvga->accel.tvga_pattern[y][1], tvga->accel.tvga_pattern[y][2], tvga->accel.tvga_pattern[y][3], tvga->accel.tvga_pattern[y][4], tvga->accel.tvga_pattern[y][5], tvga->accel.tvga_pattern[y][6], tvga->accel.tvga_pattern[y][7]); - } - if (count == -1) pclog("Command %i %i\n", tvga->accel.command, TGUI_BITBLT); - switch (tvga->accel.command) + }*/ +// if (count == -1) pclog("Command %i %i %p\n", tvga->accel.command, TGUI_BITBLT, tvga); + switch (tvga->accel.command) { case TGUI_BITBLT: - if (count == -1) pclog("BITBLT src %i,%i dst %i,%i size %i,%i flags %04X\n", tvga->accel.src_x, tvga->accel.src_y, tvga->accel.dst_x, tvga->accel.dst_y, tvga->accel.size_x, tvga->accel.size_y, tvga->accel.flags); +// if (count == -1) pclog("BITBLT src %i,%i dst %i,%i size %i,%i flags %04X\n", tvga->accel.src_x, tvga->accel.src_y, tvga->accel.dst_x, tvga->accel.dst_y, tvga->accel.size_x, tvga->accel.size_y, tvga->accel.flags); if (count == -1) { tvga->accel.src = tvga->accel.src_old = tvga->accel.src_x + (tvga->accel.src_y * tvga->accel.pitch); @@ -571,17 +583,16 @@ void tvga_accel_command(int count, uint32_t cpu_dat, tvga_t *tvga) case TGUI_SRCCPU: if (count == -1) { -// pclog("Blit start\n"); +// pclog("Blit start TGUI_SRCCPU\n"); if (svga->crtc[0x21] & 0x20) - { - mem_removehandler(tvga->linear_base, tvga->linear_size, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, NULL); - mem_sethandler(tvga->linear_base, tvga->linear_size, svga_read_linear, svga_readw_linear, svga_readl_linear, tvga_accel_write_fb_b, tvga_accel_write_fb_w, tvga_accel_write_fb_l, NULL); - } + mem_mapping_set_handler(&tvga->linear_mapping, svga_read_linear, svga_readw_linear, svga_readl_linear, tvga_accel_write_fb_b, tvga_accel_write_fb_w, tvga_accel_write_fb_l); + if (tvga->accel.use_src) return; } else count >>= 3; +// pclog("TGUI_SRCCPU\n"); while (count) { if (tvga->accel.bpp == 0) @@ -628,8 +639,7 @@ void tvga_accel_command(int count, uint32_t cpu_dat, tvga_t *tvga) if (svga->crtc[0x21] & 0x20) { // pclog("Blit end\n"); - mem_removehandler(tvga->linear_base, tvga->linear_size, svga_read_linear, svga_readw_linear, svga_readl_linear, tvga_accel_write_fb_b, tvga_accel_write_fb_w, tvga_accel_write_fb_l, NULL); - mem_sethandler(tvga->linear_base, tvga->linear_size, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, NULL); + mem_mapping_set_handler(&tvga->linear_mapping, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear); } return; } @@ -643,12 +653,11 @@ void tvga_accel_command(int count, uint32_t cpu_dat, tvga_t *tvga) case TGUI_SRCMONO | TGUI_SRCCPU: if (count == -1) { -// pclog("Blit start\n"); +// pclog("Blit start TGUI_SRCMONO | TGUI_SRCCPU\n"); if (svga->crtc[0x21] & 0x20) - { - mem_removehandler(tvga->linear_base, tvga->linear_size, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, NULL); - mem_sethandler(tvga->linear_base, tvga->linear_size, svga_read_linear, svga_readw_linear, svga_readl_linear, tvga_accel_write_fb_b, tvga_accel_write_fb_w, tvga_accel_write_fb_l, NULL); - } + mem_mapping_set_handler(&tvga->linear_mapping, svga_read_linear, svga_readw_linear, svga_readl_linear, tvga_accel_write_fb_b, tvga_accel_write_fb_w, tvga_accel_write_fb_l); + +// pclog(" %i\n", tvga->accel.command); if (tvga->accel.use_src) return; } @@ -691,8 +700,7 @@ void tvga_accel_command(int count, uint32_t cpu_dat, tvga_t *tvga) if (svga->crtc[0x21] & 0x20) { // pclog("Blit end\n"); - mem_removehandler(tvga->linear_base, tvga->linear_size, svga_read_linear, svga_readw_linear, svga_readl_linear, tvga_accel_write_fb_b, tvga_accel_write_fb_w, tvga_accel_write_fb_l, NULL); - mem_sethandler(tvga->linear_base, tvga->linear_size, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, NULL); + mem_mapping_set_handler(&tvga->linear_mapping, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear); } return; } @@ -748,7 +756,7 @@ void tvga_accel_command(int count, uint32_t cpu_dat, tvga_t *tvga) void tvga_accel_write(uint32_t addr, uint8_t val, void *p) { tvga_t *tvga = (tvga_t *)p; - pclog("tvga_accel_write : %08X %02X %04X(%08X):%08X %02X\n", addr, val, CS,cs,pc, opcode); +// pclog("tvga_accel_write : %08X %02X %04X(%08X):%08X %02X\n", addr, val, CS,cs,pc, opcode); if ((addr & ~0xff) != 0xbff00) return; switch (addr & 0xff) @@ -875,7 +883,7 @@ void tvga_accel_write(uint32_t addr, uint8_t val, void *p) void tvga_accel_write_w(uint32_t addr, uint16_t val, void *p) { tvga_t *tvga = (tvga_t *)p; - pclog("tvga_accel_write_w %08X %04X\n", addr, val); +// pclog("tvga_accel_write_w %08X %04X\n", addr, val); tvga_accel_write(addr, val, tvga); tvga_accel_write(addr + 1, val >> 8, tvga); } @@ -883,7 +891,7 @@ void tvga_accel_write_w(uint32_t addr, uint16_t val, void *p) void tvga_accel_write_l(uint32_t addr, uint32_t val, void *p) { tvga_t *tvga = (tvga_t *)p; - pclog("tvga_accel_write_l %08X %08X\n", addr, val); +// pclog("tvga_accel_write_l %08X %08X\n", addr, val); tvga_accel_write(addr, val, tvga); tvga_accel_write(addr + 1, val >> 8, tvga); tvga_accel_write(addr + 2, val >> 16, tvga); @@ -989,34 +997,37 @@ uint8_t tvga_accel_read(uint32_t addr, void *p) uint16_t tvga_accel_read_w(uint32_t addr, void *p) { tvga_t *tvga = (tvga_t *)p; - pclog("tvga_accel_read_w %08X\n", addr); +// pclog("tvga_accel_read_w %08X\n", addr); return tvga_accel_read(addr, tvga) | (tvga_accel_read(addr + 1, tvga) << 8); } uint32_t tvga_accel_read_l(uint32_t addr, void *p) { tvga_t *tvga = (tvga_t *)p; - pclog("tvga_accel_read_l %08X\n", addr); +// pclog("tvga_accel_read_l %08X\n", addr); return tvga_accel_read_w(addr, tvga) | (tvga_accel_read_w(addr + 2, tvga) << 16); } void tvga_accel_write_fb_b(uint32_t addr, uint8_t val, void *p) { - tvga_t *tvga = (tvga_t *)p; + svga_t *svga = (svga_t *)p; + tvga_t *tvga = (tvga_t *)svga->p; // pclog("tvga_accel_write_fb_b %08X %02X\n", addr, val); tvga_accel_command(8, val << 24, tvga); } void tvga_accel_write_fb_w(uint32_t addr, uint16_t val, void *p) { - tvga_t *tvga = (tvga_t *)p; + svga_t *svga = (svga_t *)p; + tvga_t *tvga = (tvga_t *)svga->p; // pclog("tvga_accel_write_fb_w %08X %04X\n", addr, val); tvga_accel_command(16, (((val & 0xff00) >> 8) | ((val & 0x00ff) << 8)) << 16, tvga); } void tvga_accel_write_fb_l(uint32_t addr, uint32_t val, void *p) { - tvga_t *tvga = (tvga_t *)p; + svga_t *svga = (svga_t *)p; + tvga_t *tvga = (tvga_t *)svga->p; // pclog("tvga_accel_write_fb_l %08X %08X\n", addr, val); tvga_accel_command(32, ((val & 0xff000000) >> 24) | ((val & 0x00ff0000) >> 8) | ((val & 0x0000ff00) << 8) | ((val & 0x000000ff) << 24), tvga); } diff --git a/src/vid_unk_ramdac.c b/src/vid_unk_ramdac.c index 1812a31..d21038e 100644 --- a/src/vid_unk_ramdac.c +++ b/src/vid_unk_ramdac.c @@ -2,6 +2,7 @@ It is possibly a Sierra 1502x It's addressed by the TLIVESA1 driver for ET4000*/ #include "ibm.h" +#include "mem.h" #include "video.h" #include "vid_svga.h" #include "vid_unk_ramdac.h" diff --git a/src/vid_vga.c b/src/vid_vga.c index 625139d..e9bfb9c 100644 --- a/src/vid_vga.c +++ b/src/vid_vga.c @@ -3,6 +3,7 @@ #include "ibm.h" #include "device.h" #include "io.h" +#include "mem.h" #include "video.h" #include "vid_svga.h" #include "vid_vga.h" diff --git a/src/vid_voodoo.c b/src/vid_voodoo.c index 2f216aa..b8d5434 100644 --- a/src/vid_voodoo.c +++ b/src/vid_voodoo.c @@ -8,6 +8,10 @@ static int tris = 0; static struct voodoo { + mem_mapping_t mmio_mapping; + mem_mapping_t fb_mapping; + mem_mapping_t tex_mapping; + int pci_enable; uint32_t color0, color1; @@ -669,18 +673,20 @@ static void voodoo_tex_writel(uint32_t addr, uint32_t val, void *priv) static void voodoo_recalcmapping() { - mem_removehandler(0x00000000, 0xffffffff, NULL, NULL, voodoo_readl, NULL, NULL, voodoo_writel, NULL); - mem_removehandler(0x00000000, 0xffffffff, NULL, voodoo_fb_readw, voodoo_fb_readl, NULL, voodoo_fb_writew, voodoo_fb_writel, NULL); - mem_removehandler(0x00000000, 0xffffffff, NULL, NULL, NULL, NULL, voodoo_tex_writew, voodoo_tex_writel, NULL); if (voodoo.pci_enable) { pclog("voodoo_recalcmapping : memBaseAddr %08X\n", voodoo.memBaseAddr); - mem_sethandler(voodoo.memBaseAddr, 0x003fffff, NULL, NULL, voodoo_readl, NULL, NULL, voodoo_writel, NULL); - mem_sethandler(voodoo.memBaseAddr + 0x00400000, 0x003fffff, NULL, voodoo_fb_readw, voodoo_fb_readl, NULL, voodoo_fb_writew, voodoo_fb_writel, NULL); - mem_sethandler(voodoo.memBaseAddr + 0x00800000, 0x007fffff, NULL, NULL, NULL, NULL, voodoo_tex_writew, voodoo_tex_writel, NULL); + mem_mapping_set_addr(&voodoo.mmio_mapping, voodoo.memBaseAddr, 0x00400000); + mem_mapping_set_addr(&voodoo.fb_mapping, voodoo.memBaseAddr + 0x00400000, 0x00400000); + mem_mapping_set_addr(&voodoo.tex_mapping, voodoo.memBaseAddr + 0x00800000, 0x00800000); } else + { pclog("voodoo_recalcmapping : disabled\n"); + mem_mapping_disable(&voodoo.mmio_mapping); + mem_mapping_disable(&voodoo.fb_mapping); + mem_mapping_disable(&voodoo.tex_mapping); + } } uint8_t voodoo_pci_read(int func, int addr, void *priv) @@ -727,6 +733,11 @@ void voodoo_init() return; voodoo_make_dither(); pci_add(voodoo_pci_read, voodoo_pci_write, NULL); + + mem_mapping_add(&voodoo.mmio_mapping, 0, 0, NULL, NULL, voodoo_readl, NULL, NULL, voodoo_writel, NULL); + mem_mapping_add(&voodoo.fb_mapping, 0, 0, NULL, voodoo_fb_readw, voodoo_fb_readl, NULL, voodoo_fb_writew, voodoo_fb_writel, NULL); + mem_mapping_add(&voodoo.tex_mapping, 0, 0, NULL, NULL, NULL, NULL, voodoo_tex_writew, voodoo_tex_writel, NULL); + voodoo.fb_mem = malloc(2 * 1024 * 1024); voodoo.tex_mem = malloc(2 * 1024 * 1024); } diff --git a/src/video.c b/src/video.c index c085d56..775de27 100644 --- a/src/video.c +++ b/src/video.c @@ -3,6 +3,7 @@ #include #include "ibm.h" #include "device.h" +#include "mem.h" #include "video.h" #include "vid_svga.h" #include "io.h"