From 6d95f00c3624834578946c7984e73ce5de8f25a2 Mon Sep 17 00:00:00 2001
From: TomW <TomW@localhost>
Date: Wed, 20 May 2015 20:52:42 +0100
Subject: [PATCH] POP SS correctly disables interrupts on the next instruction.

---
 src/x86_ops_stack.h | 41 ++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 40 insertions(+), 1 deletion(-)

diff --git a/src/x86_ops_stack.h b/src/x86_ops_stack.h
index edb9424..f184d1b 100644
--- a/src/x86_ops_stack.h
+++ b/src/x86_ops_stack.h
@@ -434,4 +434,43 @@ POP_SEG_OPS(DS, &_ds);
 POP_SEG_OPS(ES, &_es);
 POP_SEG_OPS(FS, &_fs);
 POP_SEG_OPS(GS, &_gs);
-POP_SEG_OPS(SS, &_ss);
+
+
+static int opPOP_SS_w(uint32_t fetchdat)
+{
+        uint16_t temp_seg;
+        uint32_t temp_esp = ESP;
+        temp_seg = POP_W();                     if (abrt) return 1;
+        loadseg(temp_seg, &_ss);                if (abrt) ESP = temp_esp;
+        CLOCK_CYCLES(is486 ? 3 : 7);
+        
+        oldpc = pc;
+        op32 = use32;
+        ssegs = 0;
+        ea_seg = &_ds;
+        fetchdat = fastreadl(cs + pc);
+        pc++;
+        if (abrt) return 1;
+        x86_opcodes[(fetchdat & 0xff) | op32](fetchdat >> 8);
+
+        return 1;
+}
+static int opPOP_SS_l(uint32_t fetchdat)
+{
+        uint32_t temp_seg;
+        uint32_t temp_esp = ESP;
+        temp_seg = POP_L();                     if (abrt) return 1;
+        loadseg(temp_seg & 0xffff, &_ss);       if (abrt) ESP = temp_esp;
+        CLOCK_CYCLES(is486 ? 3 : 7);
+
+        oldpc = pc;
+        op32 = use32;
+        ssegs = 0;
+        ea_seg = &_ds;
+        fetchdat = fastreadl(cs + pc);
+        pc++;
+        if (abrt) return 1;
+        x86_opcodes[(fetchdat & 0xff) | op32](fetchdat >> 8);
+
+        return 1;
+}