Fixed lazy V flag on SHL/SHR/SAR - IBM AT & Acer 386 BIOSes work again.
This commit is contained in:
TomW
parent
2c1e691c1a
commit
6c7b746bf9
2 changed files with 351 additions and 276 deletions
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@ -12,7 +12,19 @@ enum
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FLAGS_SUB8,
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FLAGS_SUB8,
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FLAGS_SUB16,
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FLAGS_SUB16,
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FLAGS_SUB32
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FLAGS_SUB32,
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FLAGS_SHL8,
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FLAGS_SHL16,
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FLAGS_SHL32,
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FLAGS_SHR8,
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FLAGS_SHR16,
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FLAGS_SHR32,
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FLAGS_SAR8,
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FLAGS_SAR16,
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FLAGS_SAR32,
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};
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};
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static int flags_op;
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static int flags_op;
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@ -32,6 +44,15 @@ static inline int ZF_SET()
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case FLAGS_SUB8:
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case FLAGS_SUB8:
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case FLAGS_SUB16:
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case FLAGS_SUB16:
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case FLAGS_SUB32:
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case FLAGS_SUB32:
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case FLAGS_SHL8:
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case FLAGS_SHL16:
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case FLAGS_SHL32:
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case FLAGS_SHR8:
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case FLAGS_SHR16:
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case FLAGS_SHR32:
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case FLAGS_SAR8:
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case FLAGS_SAR16:
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case FLAGS_SAR32:
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return !flags_res;
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return !flags_res;
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case FLAGS_UNKNOWN:
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case FLAGS_UNKNOWN:
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@ -46,16 +67,25 @@ static inline int NF_SET()
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case FLAGS_ZN8:
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case FLAGS_ZN8:
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case FLAGS_ADD8:
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case FLAGS_ADD8:
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case FLAGS_SUB8:
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case FLAGS_SUB8:
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case FLAGS_SHL8:
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case FLAGS_SHR8:
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case FLAGS_SAR8:
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return flags_res & 0x80;
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return flags_res & 0x80;
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case FLAGS_ZN16:
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case FLAGS_ZN16:
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case FLAGS_ADD16:
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case FLAGS_ADD16:
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case FLAGS_SUB16:
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case FLAGS_SUB16:
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case FLAGS_SHL16:
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case FLAGS_SHR16:
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case FLAGS_SAR16:
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return flags_res & 0x8000;
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return flags_res & 0x8000;
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case FLAGS_ZN32:
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case FLAGS_ZN32:
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case FLAGS_ADD32:
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case FLAGS_ADD32:
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case FLAGS_SUB32:
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case FLAGS_SUB32:
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case FLAGS_SHL32:
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case FLAGS_SHR32:
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case FLAGS_SAR32:
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return flags_res & 0x80000000;
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return flags_res & 0x80000000;
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case FLAGS_UNKNOWN:
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case FLAGS_UNKNOWN:
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@ -76,6 +106,15 @@ static inline int PF_SET()
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case FLAGS_SUB8:
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case FLAGS_SUB8:
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case FLAGS_SUB16:
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case FLAGS_SUB16:
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case FLAGS_SUB32:
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case FLAGS_SUB32:
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case FLAGS_SHL8:
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case FLAGS_SHL16:
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case FLAGS_SHL32:
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case FLAGS_SHR8:
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case FLAGS_SHR16:
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case FLAGS_SHR32:
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case FLAGS_SAR8:
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case FLAGS_SAR16:
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case FLAGS_SAR32:
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return znptable8[flags_res & 0xff] & P_FLAG;
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return znptable8[flags_res & 0xff] & P_FLAG;
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case FLAGS_UNKNOWN:
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case FLAGS_UNKNOWN:
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@ -90,6 +129,9 @@ static inline int VF_SET()
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case FLAGS_ZN8:
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case FLAGS_ZN8:
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case FLAGS_ZN16:
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case FLAGS_ZN16:
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case FLAGS_ZN32:
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case FLAGS_ZN32:
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case FLAGS_SAR8:
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case FLAGS_SAR16:
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case FLAGS_SAR32:
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return 0;
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return 0;
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case FLAGS_ADD8:
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case FLAGS_ADD8:
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@ -106,6 +148,20 @@ static inline int VF_SET()
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case FLAGS_SUB32:
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case FLAGS_SUB32:
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return ((flags_op1 ^ flags_op2) & (flags_op1 ^ flags_res) & 0x80000000);
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return ((flags_op1 ^ flags_op2) & (flags_op1 ^ flags_res) & 0x80000000);
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case FLAGS_SHL8:
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return (((flags_op1 << flags_op2) ^ (flags_op1 << (flags_op2 - 1))) & 0x80);
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case FLAGS_SHL16:
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return (((flags_op1 << flags_op2) ^ (flags_op1 << (flags_op2 - 1))) & 0x8000);
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case FLAGS_SHL32:
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return (((flags_op1 << flags_op2) ^ (flags_op1 << (flags_op2 - 1))) & 0x80000000);
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case FLAGS_SHR8:
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return ((flags_op2 == 1) && (flags_op1 & 0x80));
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case FLAGS_SHR16:
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return ((flags_op2 == 1) && (flags_op1 & 0x8000));
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case FLAGS_SHR32:
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return ((flags_op2 == 1) && (flags_op1 & 0x80000000));
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case FLAGS_UNKNOWN:
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case FLAGS_UNKNOWN:
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return flags & V_FLAG;
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return flags & V_FLAG;
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}
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}
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@ -118,6 +174,15 @@ static inline int AF_SET()
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case FLAGS_ZN8:
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case FLAGS_ZN8:
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case FLAGS_ZN16:
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case FLAGS_ZN16:
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case FLAGS_ZN32:
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case FLAGS_ZN32:
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case FLAGS_SHL8:
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case FLAGS_SHL16:
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case FLAGS_SHL32:
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case FLAGS_SHR8:
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case FLAGS_SHR16:
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case FLAGS_SHR32:
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case FLAGS_SAR8:
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case FLAGS_SAR16:
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case FLAGS_SAR32:
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return 0;
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return 0;
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case FLAGS_ADD8:
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case FLAGS_ADD8:
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@ -214,6 +279,13 @@ static inline void setznp32(uint32_t val)
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flags &= ~C_FLAG;
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flags &= ~C_FLAG;
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}
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}
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#define set_flags_shift(op, orig, shift, res) \
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flags_op = op; \
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flags_res = res; \
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flags_op1 = orig; \
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flags_op2 = shift; \
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flags &= ~C_FLAG;
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static inline void setadd8(uint8_t a, uint8_t b)
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static inline void setadd8(uint8_t a, uint8_t b)
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{
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{
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flags_op1 = a;
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flags_op1 = a;
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@ -1,280 +1,283 @@
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#define OP_SHIFT_b(c) \
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#define OP_SHIFT_b(c) \
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if (!c) return 0; \
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{ \
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flags_rebuild(); \
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uint8_t temp_orig = temp; \
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switch (rmdat & 0x38) \
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if (!c) return 0; \
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{ \
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flags_rebuild(); \
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case 0x00: /*ROL b, c*/ \
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switch (rmdat & 0x38) \
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while (c > 0) \
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{ \
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{ \
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case 0x00: /*ROL b, c*/ \
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temp2 = (temp & 0x80) ? 1 : 0; \
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while (c > 0) \
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temp = (temp << 1) | temp2; \
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{ \
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c--; \
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temp2 = (temp & 0x80) ? 1 : 0; \
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} \
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temp = (temp << 1) | temp2; \
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seteab(temp); if (abrt) return 0; \
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c--; \
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flags &= ~(C_FLAG | V_FLAG); \
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} \
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if (temp2) flags |= C_FLAG; \
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seteab(temp); if (abrt) return 0; \
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if ((flags & C_FLAG) ^ (temp >> 7)) flags |= V_FLAG; \
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flags &= ~(C_FLAG | V_FLAG); \
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cycles -= ((mod == 3) ? 3 : 7); \
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if (temp2) flags |= C_FLAG; \
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break; \
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if ((flags & C_FLAG) ^ (temp >> 7)) flags |= V_FLAG; \
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case 0x08: /*ROR b,CL*/ \
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cycles -= ((mod == 3) ? 3 : 7); \
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while (c > 0) \
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break; \
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{ \
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case 0x08: /*ROR b,CL*/ \
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temp2 = temp & 1; \
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while (c > 0) \
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temp >>= 1; \
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{ \
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if (temp2) temp |= 0x80; \
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temp2 = temp & 1; \
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c--; \
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temp >>= 1; \
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} \
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if (temp2) temp |= 0x80; \
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seteab(temp); if (abrt) return 0; \
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c--; \
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flags &= ~(C_FLAG | V_FLAG); \
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} \
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if (temp2) flags |= C_FLAG; \
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seteab(temp); if (abrt) return 0; \
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if ((temp ^ (temp >> 1)) & 0x40) flags |= V_FLAG; \
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flags &= ~(C_FLAG | V_FLAG); \
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cycles -= ((mod == 3) ? 3 : 7); \
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if (temp2) flags |= C_FLAG; \
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break; \
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if ((temp ^ (temp >> 1)) & 0x40) flags |= V_FLAG; \
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case 0x10: /*RCL b,CL*/ \
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cycles -= ((mod == 3) ? 3 : 7); \
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temp2 = flags & C_FLAG; \
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break; \
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while (c > 0) \
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case 0x10: /*RCL b,CL*/ \
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{ \
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temp2 = flags & C_FLAG; \
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tempc = temp2 ? 1 : 0; \
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while (c > 0) \
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temp2 = temp & 0x80; \
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{ \
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temp = (temp << 1) | tempc; \
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tempc = temp2 ? 1 : 0; \
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c--; \
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temp2 = temp & 0x80; \
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if (is486) cycles--; \
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temp = (temp << 1) | tempc; \
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} \
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c--; \
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seteab(temp); if (abrt) return 0; \
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if (is486) cycles--; \
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flags &= ~(C_FLAG | V_FLAG); \
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} \
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if (temp2) flags |= C_FLAG; \
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seteab(temp); if (abrt) return 0; \
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if ((flags & C_FLAG) ^ (temp >> 7)) flags |= V_FLAG; \
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flags &= ~(C_FLAG | V_FLAG); \
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cycles -= ((mod == 3) ? 9 : 10); \
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if (temp2) flags |= C_FLAG; \
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break; \
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if ((flags & C_FLAG) ^ (temp >> 7)) flags |= V_FLAG; \
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case 0x18: /*RCR b,CL*/ \
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cycles -= ((mod == 3) ? 9 : 10); \
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temp2 = flags & C_FLAG; \
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break; \
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while (c > 0) \
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case 0x18: /*RCR b,CL*/ \
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{ \
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temp2 = flags & C_FLAG; \
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tempc = temp2 ? 0x80 : 0; \
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while (c > 0) \
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temp2 = temp & 1; \
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{ \
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temp = (temp >> 1) | tempc; \
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tempc = temp2 ? 0x80 : 0; \
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c--; \
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temp2 = temp & 1; \
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if (is486) cycles--; \
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temp = (temp >> 1) | tempc; \
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} \
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c--; \
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seteab(temp); if (abrt) return 0; \
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if (is486) cycles--; \
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flags &= ~(C_FLAG | V_FLAG); \
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} \
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if (temp2) flags |= C_FLAG; \
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seteab(temp); if (abrt) return 0; \
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if ((temp ^ (temp >> 1)) & 0x40) flags |= V_FLAG; \
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flags &= ~(C_FLAG | V_FLAG); \
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cycles -= ((mod == 3) ? 9 : 10); \
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if (temp2) flags |= C_FLAG; \
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break; \
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if ((temp ^ (temp >> 1)) & 0x40) flags |= V_FLAG; \
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case 0x20: case 0x30: /*SHL b,CL*/ \
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cycles -= ((mod == 3) ? 9 : 10); \
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seteab(temp << c); if (abrt) return 0; \
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break; \
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setznp8(temp << c); \
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case 0x20: case 0x30: /*SHL b,CL*/ \
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if ((temp << (c - 1)) & 0x80) flags |= C_FLAG; \
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seteab(temp << c); if (abrt) return 0; \
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if (((temp << c) ^ (temp << (c - 1))) & 0x80) flags |= V_FLAG; \
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set_flags_shift(FLAGS_SHL8, temp_orig, c, temp << c); \
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cycles -= ((mod == 3) ? 3 : 7); \
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if ((temp << (c - 1)) & 0x80) flags |= C_FLAG; \
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break; \
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cycles -= ((mod == 3) ? 3 : 7); \
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case 0x28: /*SHR b,CL*/ \
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break; \
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seteab(temp >> c); if (abrt) return 0; \
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case 0x28: /*SHR b,CL*/ \
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setznp8(temp >> c); \
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seteab(temp >> c); if (abrt) return 0; \
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if ((temp >> (c - 1)) & 1) flags |= C_FLAG; \
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set_flags_shift(FLAGS_SHR8, temp_orig, c, temp >> c); \
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if (c == 1 && temp & 0x80) flags |= V_FLAG; \
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if ((temp >> (c - 1)) & 1) flags |= C_FLAG; \
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cycles -= ((mod == 3) ? 3 : 7); \
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cycles -= ((mod == 3) ? 3 : 7); \
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break; \
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break; \
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case 0x38: /*SAR b,CL*/ \
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case 0x38: /*SAR b,CL*/ \
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tempc = ((temp >> (c - 1)) & 1); \
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tempc = ((temp >> (c - 1)) & 1); \
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while (c > 0) \
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while (c > 0) \
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{ \
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{ \
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temp >>= 1; \
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temp >>= 1; \
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if (temp & 0x40) temp |= 0x80; \
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if (temp & 0x40) temp |= 0x80; \
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c--; \
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c--; \
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} \
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} \
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seteab(temp); if (abrt) return 0; \
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seteab(temp); if (abrt) return 0; \
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setznp8(temp); \
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set_flags_shift(FLAGS_SAR8, temp_orig, c, temp); \
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if (tempc) flags |= C_FLAG; \
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if (tempc) flags |= C_FLAG; \
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cycles -= ((mod == 3) ? 3 : 7); \
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cycles -= ((mod == 3) ? 3 : 7); \
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break; \
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break; \
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} \
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}
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}
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#define OP_SHIFT_w(c) \
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#define OP_SHIFT_w(c) \
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if (!c) return 0; \
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{ \
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flags_rebuild(); \
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uint16_t temp_orig = temp; \
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switch (rmdat & 0x38) \
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if (!c) return 0; \
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{ \
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flags_rebuild(); \
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case 0x00: /*ROL w, c*/ \
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switch (rmdat & 0x38) \
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while (c > 0) \
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{ \
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{ \
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case 0x00: /*ROL w, c*/ \
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temp2 = (temp & 0x8000) ? 1 : 0; \
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while (c > 0) \
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temp = (temp << 1) | temp2; \
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{ \
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c--; \
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temp2 = (temp & 0x8000) ? 1 : 0; \
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} \
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temp = (temp << 1) | temp2; \
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seteaw(temp); if (abrt) return 0; \
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c--; \
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flags &= ~(C_FLAG | V_FLAG); \
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} \
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if (temp2) flags |= C_FLAG; \
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seteaw(temp); if (abrt) return 0; \
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if ((flags & C_FLAG) ^ (temp >> 15)) flags |= V_FLAG; \
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flags &= ~(C_FLAG | V_FLAG); \
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cycles -= ((mod == 3) ? 3 : 7); \
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if (temp2) flags |= C_FLAG; \
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break; \
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if ((flags & C_FLAG) ^ (temp >> 15)) flags |= V_FLAG; \
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case 0x08: /*ROR w, c*/ \
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cycles -= ((mod == 3) ? 3 : 7); \
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while (c > 0) \
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break; \
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{ \
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case 0x08: /*ROR w, c*/ \
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temp2 = temp & 1; \
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while (c > 0) \
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temp >>= 1; \
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{ \
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if (temp2) temp |= 0x8000; \
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temp2 = temp & 1; \
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c--; \
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temp >>= 1; \
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} \
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if (temp2) temp |= 0x8000; \
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seteaw(temp); if (abrt) return 0; \
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c--; \
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flags &= ~(C_FLAG | V_FLAG); \
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} \
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if (temp2) flags |= C_FLAG; \
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seteaw(temp); if (abrt) return 0; \
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if ((temp ^ (temp >> 1)) & 0x4000) flags |= V_FLAG; \
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flags &= ~(C_FLAG | V_FLAG); \
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cycles -= ((mod == 3) ? 3 : 7); \
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if (temp2) flags |= C_FLAG; \
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break; \
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if ((temp ^ (temp >> 1)) & 0x4000) flags |= V_FLAG; \
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case 0x10: /*RCL w, c*/ \
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cycles -= ((mod == 3) ? 3 : 7); \
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temp2 = flags & C_FLAG; \
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break; \
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while (c > 0) \
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case 0x10: /*RCL w, c*/ \
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{ \
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temp2 = flags & C_FLAG; \
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tempc = temp2 ? 1 : 0; \
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while (c > 0) \
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temp2 = temp & 0x8000; \
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{ \
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temp = (temp << 1) | tempc; \
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tempc = temp2 ? 1 : 0; \
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c--; \
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temp2 = temp & 0x8000; \
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if (is486) cycles--; \
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temp = (temp << 1) | tempc; \
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} \
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c--; \
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seteaw(temp); if (abrt) return 0; \
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if (is486) cycles--; \
|
||||||
flags &= ~(C_FLAG | V_FLAG); \
|
} \
|
||||||
if (temp2) flags |= C_FLAG; \
|
seteaw(temp); if (abrt) return 0; \
|
||||||
if ((flags & C_FLAG) ^ (temp >> 15)) flags |= V_FLAG; \
|
flags &= ~(C_FLAG | V_FLAG); \
|
||||||
cycles -= ((mod == 3) ? 9 : 10); \
|
if (temp2) flags |= C_FLAG; \
|
||||||
break; \
|
if ((flags & C_FLAG) ^ (temp >> 15)) flags |= V_FLAG; \
|
||||||
case 0x18: /*RCR w, c*/ \
|
cycles -= ((mod == 3) ? 9 : 10); \
|
||||||
temp2 = flags & C_FLAG; \
|
break; \
|
||||||
while (c > 0) \
|
case 0x18: /*RCR w, c*/ \
|
||||||
{ \
|
temp2 = flags & C_FLAG; \
|
||||||
tempc = temp2 ? 0x8000 : 0; \
|
while (c > 0) \
|
||||||
temp2 = temp & 1; \
|
{ \
|
||||||
temp = (temp >> 1) | tempc; \
|
tempc = temp2 ? 0x8000 : 0; \
|
||||||
c--; \
|
temp2 = temp & 1; \
|
||||||
if (is486) cycles--; \
|
temp = (temp >> 1) | tempc; \
|
||||||
} \
|
c--; \
|
||||||
seteaw(temp); if (abrt) return 0; \
|
if (is486) cycles--; \
|
||||||
flags &= ~(C_FLAG | V_FLAG); \
|
} \
|
||||||
if (temp2) flags |= C_FLAG; \
|
seteaw(temp); if (abrt) return 0; \
|
||||||
if ((temp ^ (temp >> 1)) & 0x4000) flags |= V_FLAG; \
|
flags &= ~(C_FLAG | V_FLAG); \
|
||||||
cycles -= ((mod == 3) ? 9 : 10); \
|
if (temp2) flags |= C_FLAG; \
|
||||||
break; \
|
if ((temp ^ (temp >> 1)) & 0x4000) flags |= V_FLAG; \
|
||||||
case 0x20: case 0x30: /*SHL w, c*/ \
|
cycles -= ((mod == 3) ? 9 : 10); \
|
||||||
seteaw(temp << c); if (abrt) return 0; \
|
break; \
|
||||||
setznp16(temp << c); \
|
case 0x20: case 0x30: /*SHL w, c*/ \
|
||||||
if ((temp << (c - 1)) & 0x8000) flags |= C_FLAG; \
|
seteaw(temp << c); if (abrt) return 0; \
|
||||||
if (((temp << c) ^ (temp << (c - 1))) & 0x8000) flags |= V_FLAG;\
|
set_flags_shift(FLAGS_SHL16, temp_orig, c, temp << c); \
|
||||||
cycles -= ((mod == 3) ? 3 : 7); \
|
if ((temp << (c - 1)) & 0x8000) flags |= C_FLAG; \
|
||||||
break; \
|
cycles -= ((mod == 3) ? 3 : 7); \
|
||||||
case 0x28: /*SHR w, c*/ \
|
break; \
|
||||||
seteaw(temp >> c); if (abrt) return 0; \
|
case 0x28: /*SHR w, c*/ \
|
||||||
setznp16(temp >> c); \
|
seteaw(temp >> c); if (abrt) return 0; \
|
||||||
if ((temp >> (c - 1)) & 1) flags |= C_FLAG; \
|
set_flags_shift(FLAGS_SHR16, temp_orig, c, temp >> c); \
|
||||||
if (c == 1 && temp & 0x8000) flags |= V_FLAG; \
|
if ((temp >> (c - 1)) & 1) flags |= C_FLAG; \
|
||||||
cycles -= ((mod == 3) ? 3 : 7); \
|
cycles -= ((mod == 3) ? 3 : 7); \
|
||||||
break; \
|
break; \
|
||||||
case 0x38: /*SAR w, c*/ \
|
case 0x38: /*SAR w, c*/ \
|
||||||
tempc = ((temp >> (c - 1)) & 1); \
|
tempc = ((temp >> (c - 1)) & 1); \
|
||||||
while (c > 0) \
|
while (c > 0) \
|
||||||
{ \
|
{ \
|
||||||
temp >>= 1; \
|
temp >>= 1; \
|
||||||
if (temp & 0x4000) temp |= 0x8000; \
|
if (temp & 0x4000) temp |= 0x8000; \
|
||||||
c--; \
|
c--; \
|
||||||
} \
|
} \
|
||||||
seteaw(temp); if (abrt) return 0; \
|
seteaw(temp); if (abrt) return 0; \
|
||||||
setznp16(temp); \
|
set_flags_shift(FLAGS_SAR16, temp_orig, c, temp); \
|
||||||
if (tempc) flags |= C_FLAG; \
|
if (tempc) flags |= C_FLAG; \
|
||||||
cycles -= ((mod == 3) ? 3 : 7); \
|
cycles -= ((mod == 3) ? 3 : 7); \
|
||||||
break; \
|
break; \
|
||||||
|
} \
|
||||||
}
|
}
|
||||||
|
|
||||||
#define OP_SHIFT_l(c) \
|
#define OP_SHIFT_l(c) \
|
||||||
if (!c) return 0; \
|
{ \
|
||||||
flags_rebuild(); \
|
uint32_t temp_orig = temp; \
|
||||||
switch (rmdat & 0x38) \
|
if (!c) return 0; \
|
||||||
{ \
|
flags_rebuild(); \
|
||||||
case 0x00: /*ROL l, c*/ \
|
switch (rmdat & 0x38) \
|
||||||
while (c > 0) \
|
{ \
|
||||||
{ \
|
case 0x00: /*ROL l, c*/ \
|
||||||
temp2 = (temp & 0x80000000) ? 1 : 0; \
|
while (c > 0) \
|
||||||
temp = (temp << 1) | temp2; \
|
{ \
|
||||||
c--; \
|
temp2 = (temp & 0x80000000) ? 1 : 0; \
|
||||||
} \
|
temp = (temp << 1) | temp2; \
|
||||||
seteal(temp); if (abrt) return 0; \
|
c--; \
|
||||||
flags &= ~(C_FLAG | V_FLAG); \
|
} \
|
||||||
if (temp2) flags |= C_FLAG; \
|
seteal(temp); if (abrt) return 0; \
|
||||||
if ((flags & C_FLAG) ^ (temp >> 31)) flags |= V_FLAG; \
|
flags &= ~(C_FLAG | V_FLAG); \
|
||||||
cycles -= ((mod == 3) ? 3 : 7); \
|
if (temp2) flags |= C_FLAG; \
|
||||||
break; \
|
if ((flags & C_FLAG) ^ (temp >> 31)) flags |= V_FLAG; \
|
||||||
case 0x08: /*ROR l, c*/ \
|
cycles -= ((mod == 3) ? 3 : 7); \
|
||||||
while (c > 0) \
|
break; \
|
||||||
{ \
|
case 0x08: /*ROR l, c*/ \
|
||||||
temp2 = temp & 1; \
|
while (c > 0) \
|
||||||
temp >>= 1; \
|
{ \
|
||||||
if (temp2) temp |= 0x80000000; \
|
temp2 = temp & 1; \
|
||||||
c--; \
|
temp >>= 1; \
|
||||||
} \
|
if (temp2) temp |= 0x80000000; \
|
||||||
seteal(temp); if (abrt) return 0; \
|
c--; \
|
||||||
flags &= ~(C_FLAG | V_FLAG); \
|
} \
|
||||||
if (temp2) flags |= C_FLAG; \
|
seteal(temp); if (abrt) return 0; \
|
||||||
if ((temp ^ (temp >> 1)) & 0x40000000) flags |= V_FLAG; \
|
flags &= ~(C_FLAG | V_FLAG); \
|
||||||
cycles -= ((mod == 3) ? 3 : 7); \
|
if (temp2) flags |= C_FLAG; \
|
||||||
break; \
|
if ((temp ^ (temp >> 1)) & 0x40000000) flags |= V_FLAG; \
|
||||||
case 0x10: /*RCL l, c*/ \
|
cycles -= ((mod == 3) ? 3 : 7); \
|
||||||
temp2 = flags & C_FLAG; \
|
break; \
|
||||||
while (c > 0) \
|
case 0x10: /*RCL l, c*/ \
|
||||||
{ \
|
temp2 = flags & C_FLAG; \
|
||||||
tempc = temp2 ? 1 : 0; \
|
while (c > 0) \
|
||||||
temp2 = temp & 0x80000000; \
|
{ \
|
||||||
temp = (temp << 1) | tempc; \
|
tempc = temp2 ? 1 : 0; \
|
||||||
c--; \
|
temp2 = temp & 0x80000000; \
|
||||||
if (is486) cycles--; \
|
temp = (temp << 1) | tempc; \
|
||||||
} \
|
c--; \
|
||||||
seteal(temp); if (abrt) return 0; \
|
if (is486) cycles--; \
|
||||||
flags &= ~(C_FLAG | V_FLAG); \
|
} \
|
||||||
if (temp2) flags |= C_FLAG; \
|
seteal(temp); if (abrt) return 0; \
|
||||||
if ((flags & C_FLAG) ^ (temp >> 31)) flags |= V_FLAG; \
|
flags &= ~(C_FLAG | V_FLAG); \
|
||||||
cycles -= ((mod == 3) ? 9 : 10); \
|
if (temp2) flags |= C_FLAG; \
|
||||||
break; \
|
if ((flags & C_FLAG) ^ (temp >> 31)) flags |= V_FLAG; \
|
||||||
case 0x18: /*RCR l, c*/ \
|
cycles -= ((mod == 3) ? 9 : 10); \
|
||||||
temp2 = flags & C_FLAG; \
|
break; \
|
||||||
while (c > 0) \
|
case 0x18: /*RCR l, c*/ \
|
||||||
{ \
|
temp2 = flags & C_FLAG; \
|
||||||
tempc = temp2 ? 0x80000000 : 0; \
|
while (c > 0) \
|
||||||
temp2 = temp & 1; \
|
{ \
|
||||||
temp = (temp >> 1) | tempc; \
|
tempc = temp2 ? 0x80000000 : 0; \
|
||||||
c--; \
|
temp2 = temp & 1; \
|
||||||
if (is486) cycles--; \
|
temp = (temp >> 1) | tempc; \
|
||||||
} \
|
c--; \
|
||||||
seteal(temp); if (abrt) return 0; \
|
if (is486) cycles--; \
|
||||||
flags &= ~(C_FLAG | V_FLAG); \
|
} \
|
||||||
if (temp2) flags |= C_FLAG; \
|
seteal(temp); if (abrt) return 0; \
|
||||||
if ((temp ^ (temp >> 1)) & 0x40000000) flags |= V_FLAG; \
|
flags &= ~(C_FLAG | V_FLAG); \
|
||||||
cycles -= ((mod == 3) ? 9 : 10); \
|
if (temp2) flags |= C_FLAG; \
|
||||||
break; \
|
if ((temp ^ (temp >> 1)) & 0x40000000) flags |= V_FLAG; \
|
||||||
case 0x20: case 0x30: /*SHL l, c*/ \
|
cycles -= ((mod == 3) ? 9 : 10); \
|
||||||
seteal(temp << c); if (abrt) return 0; \
|
break; \
|
||||||
setznp32(temp << c); \
|
case 0x20: case 0x30: /*SHL l, c*/ \
|
||||||
if ((temp << (c - 1)) & 0x80000000) flags |= C_FLAG; \
|
seteal(temp << c); if (abrt) return 0; \
|
||||||
if (((temp << c) ^ (temp << (c - 1))) & 0x80000000) flags |= V_FLAG;\
|
set_flags_shift(FLAGS_SHL32, temp_orig, c, temp << c); \
|
||||||
cycles -= ((mod == 3) ? 3 : 7); \
|
if ((temp << (c - 1)) & 0x80000000) flags |= C_FLAG; \
|
||||||
break; \
|
cycles -= ((mod == 3) ? 3 : 7); \
|
||||||
case 0x28: /*SHR l, c*/ \
|
break; \
|
||||||
seteal(temp >> c); if (abrt) return 0; \
|
case 0x28: /*SHR l, c*/ \
|
||||||
setznp32(temp >> c); \
|
seteal(temp >> c); if (abrt) return 0; \
|
||||||
if ((temp >> (c - 1)) & 1) flags |= C_FLAG; \
|
set_flags_shift(FLAGS_SHR32, temp_orig, c, temp >> c); \
|
||||||
if (c == 1 && temp & 0x80000000) flags |= V_FLAG; \
|
if ((temp >> (c - 1)) & 1) flags |= C_FLAG; \
|
||||||
cycles -= ((mod == 3) ? 3 : 7); \
|
cycles -= ((mod == 3) ? 3 : 7); \
|
||||||
break; \
|
break; \
|
||||||
case 0x38: /*SAR l, c*/ \
|
case 0x38: /*SAR l, c*/ \
|
||||||
tempc = ((temp >> (c - 1)) & 1); \
|
tempc = ((temp >> (c - 1)) & 1); \
|
||||||
while (c > 0) \
|
while (c > 0) \
|
||||||
{ \
|
{ \
|
||||||
temp >>= 1; \
|
temp >>= 1; \
|
||||||
if (temp & 0x40000000) temp |= 0x80000000; \
|
if (temp & 0x40000000) temp |= 0x80000000; \
|
||||||
c--; \
|
c--; \
|
||||||
} \
|
} \
|
||||||
seteal(temp); if (abrt) return 0; \
|
seteal(temp); if (abrt) return 0; \
|
||||||
setznp32(temp); \
|
set_flags_shift(FLAGS_SAR32, temp_orig, c, temp); \
|
||||||
if (tempc) flags |= C_FLAG; \
|
if (tempc) flags |= C_FLAG; \
|
||||||
cycles -= ((mod == 3) ? 3 : 7); \
|
cycles -= ((mod == 3) ? 3 : 7); \
|
||||||
break; \
|
break; \
|
||||||
|
} \
|
||||||
}
|
}
|
||||||
|
|
||||||
static int opC0_a16(uint32_t fetchdat)
|
static int opC0_a16(uint32_t fetchdat)
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue