Fixed lazy V flag on SHL/SHR/SAR - IBM AT & Acer 386 BIOSes work again.
This commit is contained in:
TomW
parent
2c1e691c1a
commit
6c7b746bf9
2 changed files with 351 additions and 276 deletions
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@ -1,280 +1,283 @@
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#define OP_SHIFT_b(c) \
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if (!c) return 0; \
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flags_rebuild(); \
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switch (rmdat & 0x38) \
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{ \
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case 0x00: /*ROL b, c*/ \
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while (c > 0) \
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{ \
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temp2 = (temp & 0x80) ? 1 : 0; \
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temp = (temp << 1) | temp2; \
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c--; \
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} \
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seteab(temp); if (abrt) return 0; \
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flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) flags |= C_FLAG; \
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if ((flags & C_FLAG) ^ (temp >> 7)) flags |= V_FLAG; \
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cycles -= ((mod == 3) ? 3 : 7); \
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break; \
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case 0x08: /*ROR b,CL*/ \
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while (c > 0) \
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{ \
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temp2 = temp & 1; \
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temp >>= 1; \
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if (temp2) temp |= 0x80; \
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c--; \
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} \
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seteab(temp); if (abrt) return 0; \
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flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) flags |= C_FLAG; \
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if ((temp ^ (temp >> 1)) & 0x40) flags |= V_FLAG; \
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cycles -= ((mod == 3) ? 3 : 7); \
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break; \
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case 0x10: /*RCL b,CL*/ \
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temp2 = flags & C_FLAG; \
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while (c > 0) \
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{ \
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tempc = temp2 ? 1 : 0; \
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temp2 = temp & 0x80; \
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temp = (temp << 1) | tempc; \
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c--; \
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if (is486) cycles--; \
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} \
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seteab(temp); if (abrt) return 0; \
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flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) flags |= C_FLAG; \
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if ((flags & C_FLAG) ^ (temp >> 7)) flags |= V_FLAG; \
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cycles -= ((mod == 3) ? 9 : 10); \
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break; \
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case 0x18: /*RCR b,CL*/ \
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temp2 = flags & C_FLAG; \
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while (c > 0) \
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{ \
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tempc = temp2 ? 0x80 : 0; \
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temp2 = temp & 1; \
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temp = (temp >> 1) | tempc; \
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c--; \
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if (is486) cycles--; \
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} \
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seteab(temp); if (abrt) return 0; \
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flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) flags |= C_FLAG; \
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if ((temp ^ (temp >> 1)) & 0x40) flags |= V_FLAG; \
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cycles -= ((mod == 3) ? 9 : 10); \
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break; \
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case 0x20: case 0x30: /*SHL b,CL*/ \
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seteab(temp << c); if (abrt) return 0; \
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setznp8(temp << c); \
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if ((temp << (c - 1)) & 0x80) flags |= C_FLAG; \
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if (((temp << c) ^ (temp << (c - 1))) & 0x80) flags |= V_FLAG; \
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cycles -= ((mod == 3) ? 3 : 7); \
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break; \
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case 0x28: /*SHR b,CL*/ \
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seteab(temp >> c); if (abrt) return 0; \
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setznp8(temp >> c); \
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if ((temp >> (c - 1)) & 1) flags |= C_FLAG; \
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if (c == 1 && temp & 0x80) flags |= V_FLAG; \
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cycles -= ((mod == 3) ? 3 : 7); \
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break; \
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case 0x38: /*SAR b,CL*/ \
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tempc = ((temp >> (c - 1)) & 1); \
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while (c > 0) \
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{ \
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temp >>= 1; \
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if (temp & 0x40) temp |= 0x80; \
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c--; \
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} \
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seteab(temp); if (abrt) return 0; \
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setznp8(temp); \
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if (tempc) flags |= C_FLAG; \
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cycles -= ((mod == 3) ? 3 : 7); \
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break; \
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#define OP_SHIFT_b(c) \
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{ \
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uint8_t temp_orig = temp; \
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if (!c) return 0; \
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flags_rebuild(); \
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switch (rmdat & 0x38) \
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{ \
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case 0x00: /*ROL b, c*/ \
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while (c > 0) \
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{ \
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temp2 = (temp & 0x80) ? 1 : 0; \
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temp = (temp << 1) | temp2; \
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c--; \
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} \
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seteab(temp); if (abrt) return 0; \
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flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) flags |= C_FLAG; \
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if ((flags & C_FLAG) ^ (temp >> 7)) flags |= V_FLAG; \
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cycles -= ((mod == 3) ? 3 : 7); \
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break; \
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case 0x08: /*ROR b,CL*/ \
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while (c > 0) \
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{ \
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temp2 = temp & 1; \
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temp >>= 1; \
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if (temp2) temp |= 0x80; \
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c--; \
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} \
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seteab(temp); if (abrt) return 0; \
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flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) flags |= C_FLAG; \
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if ((temp ^ (temp >> 1)) & 0x40) flags |= V_FLAG; \
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cycles -= ((mod == 3) ? 3 : 7); \
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break; \
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case 0x10: /*RCL b,CL*/ \
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temp2 = flags & C_FLAG; \
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while (c > 0) \
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{ \
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tempc = temp2 ? 1 : 0; \
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temp2 = temp & 0x80; \
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temp = (temp << 1) | tempc; \
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c--; \
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if (is486) cycles--; \
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} \
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seteab(temp); if (abrt) return 0; \
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flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) flags |= C_FLAG; \
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if ((flags & C_FLAG) ^ (temp >> 7)) flags |= V_FLAG; \
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cycles -= ((mod == 3) ? 9 : 10); \
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break; \
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case 0x18: /*RCR b,CL*/ \
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temp2 = flags & C_FLAG; \
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while (c > 0) \
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{ \
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tempc = temp2 ? 0x80 : 0; \
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temp2 = temp & 1; \
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temp = (temp >> 1) | tempc; \
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c--; \
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if (is486) cycles--; \
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} \
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seteab(temp); if (abrt) return 0; \
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flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) flags |= C_FLAG; \
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if ((temp ^ (temp >> 1)) & 0x40) flags |= V_FLAG; \
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cycles -= ((mod == 3) ? 9 : 10); \
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break; \
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case 0x20: case 0x30: /*SHL b,CL*/ \
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seteab(temp << c); if (abrt) return 0; \
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set_flags_shift(FLAGS_SHL8, temp_orig, c, temp << c); \
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if ((temp << (c - 1)) & 0x80) flags |= C_FLAG; \
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cycles -= ((mod == 3) ? 3 : 7); \
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break; \
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case 0x28: /*SHR b,CL*/ \
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seteab(temp >> c); if (abrt) return 0; \
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set_flags_shift(FLAGS_SHR8, temp_orig, c, temp >> c); \
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if ((temp >> (c - 1)) & 1) flags |= C_FLAG; \
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cycles -= ((mod == 3) ? 3 : 7); \
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break; \
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case 0x38: /*SAR b,CL*/ \
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tempc = ((temp >> (c - 1)) & 1); \
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while (c > 0) \
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{ \
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temp >>= 1; \
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if (temp & 0x40) temp |= 0x80; \
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c--; \
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} \
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seteab(temp); if (abrt) return 0; \
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set_flags_shift(FLAGS_SAR8, temp_orig, c, temp); \
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if (tempc) flags |= C_FLAG; \
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cycles -= ((mod == 3) ? 3 : 7); \
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break; \
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} \
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}
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#define OP_SHIFT_w(c) \
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if (!c) return 0; \
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flags_rebuild(); \
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switch (rmdat & 0x38) \
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{ \
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case 0x00: /*ROL w, c*/ \
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while (c > 0) \
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{ \
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temp2 = (temp & 0x8000) ? 1 : 0; \
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temp = (temp << 1) | temp2; \
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c--; \
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} \
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seteaw(temp); if (abrt) return 0; \
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flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) flags |= C_FLAG; \
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if ((flags & C_FLAG) ^ (temp >> 15)) flags |= V_FLAG; \
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cycles -= ((mod == 3) ? 3 : 7); \
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break; \
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case 0x08: /*ROR w, c*/ \
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while (c > 0) \
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{ \
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temp2 = temp & 1; \
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temp >>= 1; \
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if (temp2) temp |= 0x8000; \
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c--; \
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} \
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seteaw(temp); if (abrt) return 0; \
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flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) flags |= C_FLAG; \
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if ((temp ^ (temp >> 1)) & 0x4000) flags |= V_FLAG; \
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cycles -= ((mod == 3) ? 3 : 7); \
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break; \
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case 0x10: /*RCL w, c*/ \
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temp2 = flags & C_FLAG; \
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while (c > 0) \
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{ \
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tempc = temp2 ? 1 : 0; \
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temp2 = temp & 0x8000; \
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temp = (temp << 1) | tempc; \
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c--; \
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if (is486) cycles--; \
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} \
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seteaw(temp); if (abrt) return 0; \
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flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) flags |= C_FLAG; \
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if ((flags & C_FLAG) ^ (temp >> 15)) flags |= V_FLAG; \
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cycles -= ((mod == 3) ? 9 : 10); \
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break; \
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case 0x18: /*RCR w, c*/ \
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temp2 = flags & C_FLAG; \
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while (c > 0) \
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{ \
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tempc = temp2 ? 0x8000 : 0; \
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temp2 = temp & 1; \
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temp = (temp >> 1) | tempc; \
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c--; \
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if (is486) cycles--; \
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} \
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seteaw(temp); if (abrt) return 0; \
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flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) flags |= C_FLAG; \
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if ((temp ^ (temp >> 1)) & 0x4000) flags |= V_FLAG; \
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cycles -= ((mod == 3) ? 9 : 10); \
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break; \
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case 0x20: case 0x30: /*SHL w, c*/ \
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seteaw(temp << c); if (abrt) return 0; \
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setznp16(temp << c); \
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if ((temp << (c - 1)) & 0x8000) flags |= C_FLAG; \
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if (((temp << c) ^ (temp << (c - 1))) & 0x8000) flags |= V_FLAG;\
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cycles -= ((mod == 3) ? 3 : 7); \
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break; \
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case 0x28: /*SHR w, c*/ \
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seteaw(temp >> c); if (abrt) return 0; \
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setznp16(temp >> c); \
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if ((temp >> (c - 1)) & 1) flags |= C_FLAG; \
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if (c == 1 && temp & 0x8000) flags |= V_FLAG; \
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cycles -= ((mod == 3) ? 3 : 7); \
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break; \
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case 0x38: /*SAR w, c*/ \
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tempc = ((temp >> (c - 1)) & 1); \
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while (c > 0) \
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{ \
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temp >>= 1; \
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if (temp & 0x4000) temp |= 0x8000; \
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c--; \
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} \
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seteaw(temp); if (abrt) return 0; \
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setznp16(temp); \
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if (tempc) flags |= C_FLAG; \
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cycles -= ((mod == 3) ? 3 : 7); \
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break; \
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#define OP_SHIFT_w(c) \
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{ \
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uint16_t temp_orig = temp; \
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if (!c) return 0; \
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flags_rebuild(); \
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switch (rmdat & 0x38) \
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{ \
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case 0x00: /*ROL w, c*/ \
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while (c > 0) \
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{ \
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temp2 = (temp & 0x8000) ? 1 : 0; \
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temp = (temp << 1) | temp2; \
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c--; \
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} \
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seteaw(temp); if (abrt) return 0; \
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flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) flags |= C_FLAG; \
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if ((flags & C_FLAG) ^ (temp >> 15)) flags |= V_FLAG; \
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cycles -= ((mod == 3) ? 3 : 7); \
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break; \
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case 0x08: /*ROR w, c*/ \
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while (c > 0) \
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{ \
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temp2 = temp & 1; \
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temp >>= 1; \
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if (temp2) temp |= 0x8000; \
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c--; \
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} \
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seteaw(temp); if (abrt) return 0; \
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flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) flags |= C_FLAG; \
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if ((temp ^ (temp >> 1)) & 0x4000) flags |= V_FLAG; \
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cycles -= ((mod == 3) ? 3 : 7); \
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break; \
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case 0x10: /*RCL w, c*/ \
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temp2 = flags & C_FLAG; \
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while (c > 0) \
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{ \
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tempc = temp2 ? 1 : 0; \
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temp2 = temp & 0x8000; \
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temp = (temp << 1) | tempc; \
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c--; \
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if (is486) cycles--; \
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} \
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seteaw(temp); if (abrt) return 0; \
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flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) flags |= C_FLAG; \
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if ((flags & C_FLAG) ^ (temp >> 15)) flags |= V_FLAG; \
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cycles -= ((mod == 3) ? 9 : 10); \
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break; \
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case 0x18: /*RCR w, c*/ \
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temp2 = flags & C_FLAG; \
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while (c > 0) \
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{ \
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tempc = temp2 ? 0x8000 : 0; \
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temp2 = temp & 1; \
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temp = (temp >> 1) | tempc; \
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c--; \
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if (is486) cycles--; \
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} \
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seteaw(temp); if (abrt) return 0; \
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flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) flags |= C_FLAG; \
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if ((temp ^ (temp >> 1)) & 0x4000) flags |= V_FLAG; \
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cycles -= ((mod == 3) ? 9 : 10); \
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break; \
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case 0x20: case 0x30: /*SHL w, c*/ \
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seteaw(temp << c); if (abrt) return 0; \
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set_flags_shift(FLAGS_SHL16, temp_orig, c, temp << c); \
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if ((temp << (c - 1)) & 0x8000) flags |= C_FLAG; \
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cycles -= ((mod == 3) ? 3 : 7); \
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break; \
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case 0x28: /*SHR w, c*/ \
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seteaw(temp >> c); if (abrt) return 0; \
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set_flags_shift(FLAGS_SHR16, temp_orig, c, temp >> c); \
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if ((temp >> (c - 1)) & 1) flags |= C_FLAG; \
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cycles -= ((mod == 3) ? 3 : 7); \
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break; \
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case 0x38: /*SAR w, c*/ \
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tempc = ((temp >> (c - 1)) & 1); \
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while (c > 0) \
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{ \
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temp >>= 1; \
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if (temp & 0x4000) temp |= 0x8000; \
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c--; \
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} \
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seteaw(temp); if (abrt) return 0; \
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set_flags_shift(FLAGS_SAR16, temp_orig, c, temp); \
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if (tempc) flags |= C_FLAG; \
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cycles -= ((mod == 3) ? 3 : 7); \
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break; \
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} \
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}
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#define OP_SHIFT_l(c) \
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if (!c) return 0; \
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flags_rebuild(); \
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switch (rmdat & 0x38) \
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{ \
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case 0x00: /*ROL l, c*/ \
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while (c > 0) \
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{ \
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temp2 = (temp & 0x80000000) ? 1 : 0; \
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temp = (temp << 1) | temp2; \
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c--; \
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} \
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seteal(temp); if (abrt) return 0; \
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flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) flags |= C_FLAG; \
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if ((flags & C_FLAG) ^ (temp >> 31)) flags |= V_FLAG; \
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cycles -= ((mod == 3) ? 3 : 7); \
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break; \
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case 0x08: /*ROR l, c*/ \
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while (c > 0) \
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{ \
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temp2 = temp & 1; \
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temp >>= 1; \
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if (temp2) temp |= 0x80000000; \
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c--; \
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} \
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seteal(temp); if (abrt) return 0; \
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flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) flags |= C_FLAG; \
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if ((temp ^ (temp >> 1)) & 0x40000000) flags |= V_FLAG; \
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cycles -= ((mod == 3) ? 3 : 7); \
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break; \
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case 0x10: /*RCL l, c*/ \
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temp2 = flags & C_FLAG; \
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while (c > 0) \
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{ \
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tempc = temp2 ? 1 : 0; \
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temp2 = temp & 0x80000000; \
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temp = (temp << 1) | tempc; \
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c--; \
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if (is486) cycles--; \
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} \
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seteal(temp); if (abrt) return 0; \
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flags &= ~(C_FLAG | V_FLAG); \
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if (temp2) flags |= C_FLAG; \
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if ((flags & C_FLAG) ^ (temp >> 31)) flags |= V_FLAG; \
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cycles -= ((mod == 3) ? 9 : 10); \
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break; \
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case 0x18: /*RCR l, c*/ \
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temp2 = flags & C_FLAG; \
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while (c > 0) \
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{ \
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tempc = temp2 ? 0x80000000 : 0; \
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temp2 = temp & 1; \
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temp = (temp >> 1) | tempc; \
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c--; \
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||||
if (is486) cycles--; \
|
||||
} \
|
||||
seteal(temp); if (abrt) return 0; \
|
||||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((temp ^ (temp >> 1)) & 0x40000000) flags |= V_FLAG; \
|
||||
cycles -= ((mod == 3) ? 9 : 10); \
|
||||
break; \
|
||||
case 0x20: case 0x30: /*SHL l, c*/ \
|
||||
seteal(temp << c); if (abrt) return 0; \
|
||||
setznp32(temp << c); \
|
||||
if ((temp << (c - 1)) & 0x80000000) flags |= C_FLAG; \
|
||||
if (((temp << c) ^ (temp << (c - 1))) & 0x80000000) flags |= V_FLAG;\
|
||||
cycles -= ((mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
case 0x28: /*SHR l, c*/ \
|
||||
seteal(temp >> c); if (abrt) return 0; \
|
||||
setznp32(temp >> c); \
|
||||
if ((temp >> (c - 1)) & 1) flags |= C_FLAG; \
|
||||
if (c == 1 && temp & 0x80000000) flags |= V_FLAG; \
|
||||
cycles -= ((mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
case 0x38: /*SAR l, c*/ \
|
||||
tempc = ((temp >> (c - 1)) & 1); \
|
||||
while (c > 0) \
|
||||
{ \
|
||||
temp >>= 1; \
|
||||
if (temp & 0x40000000) temp |= 0x80000000; \
|
||||
c--; \
|
||||
} \
|
||||
seteal(temp); if (abrt) return 0; \
|
||||
setznp32(temp); \
|
||||
if (tempc) flags |= C_FLAG; \
|
||||
cycles -= ((mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
#define OP_SHIFT_l(c) \
|
||||
{ \
|
||||
uint32_t temp_orig = temp; \
|
||||
if (!c) return 0; \
|
||||
flags_rebuild(); \
|
||||
switch (rmdat & 0x38) \
|
||||
{ \
|
||||
case 0x00: /*ROL l, c*/ \
|
||||
while (c > 0) \
|
||||
{ \
|
||||
temp2 = (temp & 0x80000000) ? 1 : 0; \
|
||||
temp = (temp << 1) | temp2; \
|
||||
c--; \
|
||||
} \
|
||||
seteal(temp); if (abrt) return 0; \
|
||||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((flags & C_FLAG) ^ (temp >> 31)) flags |= V_FLAG; \
|
||||
cycles -= ((mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
case 0x08: /*ROR l, c*/ \
|
||||
while (c > 0) \
|
||||
{ \
|
||||
temp2 = temp & 1; \
|
||||
temp >>= 1; \
|
||||
if (temp2) temp |= 0x80000000; \
|
||||
c--; \
|
||||
} \
|
||||
seteal(temp); if (abrt) return 0; \
|
||||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((temp ^ (temp >> 1)) & 0x40000000) flags |= V_FLAG; \
|
||||
cycles -= ((mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
case 0x10: /*RCL l, c*/ \
|
||||
temp2 = flags & C_FLAG; \
|
||||
while (c > 0) \
|
||||
{ \
|
||||
tempc = temp2 ? 1 : 0; \
|
||||
temp2 = temp & 0x80000000; \
|
||||
temp = (temp << 1) | tempc; \
|
||||
c--; \
|
||||
if (is486) cycles--; \
|
||||
} \
|
||||
seteal(temp); if (abrt) return 0; \
|
||||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((flags & C_FLAG) ^ (temp >> 31)) flags |= V_FLAG; \
|
||||
cycles -= ((mod == 3) ? 9 : 10); \
|
||||
break; \
|
||||
case 0x18: /*RCR l, c*/ \
|
||||
temp2 = flags & C_FLAG; \
|
||||
while (c > 0) \
|
||||
{ \
|
||||
tempc = temp2 ? 0x80000000 : 0; \
|
||||
temp2 = temp & 1; \
|
||||
temp = (temp >> 1) | tempc; \
|
||||
c--; \
|
||||
if (is486) cycles--; \
|
||||
} \
|
||||
seteal(temp); if (abrt) return 0; \
|
||||
flags &= ~(C_FLAG | V_FLAG); \
|
||||
if (temp2) flags |= C_FLAG; \
|
||||
if ((temp ^ (temp >> 1)) & 0x40000000) flags |= V_FLAG; \
|
||||
cycles -= ((mod == 3) ? 9 : 10); \
|
||||
break; \
|
||||
case 0x20: case 0x30: /*SHL l, c*/ \
|
||||
seteal(temp << c); if (abrt) return 0; \
|
||||
set_flags_shift(FLAGS_SHL32, temp_orig, c, temp << c); \
|
||||
if ((temp << (c - 1)) & 0x80000000) flags |= C_FLAG; \
|
||||
cycles -= ((mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
case 0x28: /*SHR l, c*/ \
|
||||
seteal(temp >> c); if (abrt) return 0; \
|
||||
set_flags_shift(FLAGS_SHR32, temp_orig, c, temp >> c); \
|
||||
if ((temp >> (c - 1)) & 1) flags |= C_FLAG; \
|
||||
cycles -= ((mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
case 0x38: /*SAR l, c*/ \
|
||||
tempc = ((temp >> (c - 1)) & 1); \
|
||||
while (c > 0) \
|
||||
{ \
|
||||
temp >>= 1; \
|
||||
if (temp & 0x40000000) temp |= 0x80000000; \
|
||||
c--; \
|
||||
} \
|
||||
seteal(temp); if (abrt) return 0; \
|
||||
set_flags_shift(FLAGS_SAR32, temp_orig, c, temp); \
|
||||
if (tempc) flags |= C_FLAG; \
|
||||
cycles -= ((mod == 3) ? 3 : 7); \
|
||||
break; \
|
||||
} \
|
||||
}
|
||||
|
||||
static int opC0_a16(uint32_t fetchdat)
|
||||
|
|
|
|||
Loading…
Reference in a new issue