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Fix BY16 addressing on Cirrus Logic cards.

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This commit is contained in:
SarahW 2021-05-29 09:31:21 +01:00
commit 6b80e58487
1 changed files with 15 additions and 10 deletions
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25
src/vid_cl5429.c
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@ -96,9 +96,10 @@ typedef struct gd5429_t
int vidsys_ena; int vidsys_ena;
} gd5429_t; } gd5429_t;
#define GRB_X8_ADDRESSING (1 << 1) #define GRB_X8_ADDRESSING (1 << 1)
#define GRB_WRITEMODE_EXT (1 << 2) #define GRB_WRITEMODE_EXT (1 << 2)
#define GRB_8B_LATCHES (1 << 3) #define GRB_8B_LATCHES (1 << 3)
#define GRB_ENHANCED_16BIT (1 << 4)
static void gd5429_mmio_write(uint32_t addr, uint8_t val, void *p); static void gd5429_mmio_write(uint32_t addr, uint8_t val, void *p);
static void gd5429_mmio_writew(uint32_t addr, uint16_t val, void *p); static void gd5429_mmio_writew(uint32_t addr, uint16_t val, void *p);
@ -845,7 +846,9 @@ void gd5429_write_linear(uint32_t addr, uint8_t val, void *p)
// if (svga_output) pclog("Write LFB %08X %02X ", addr, val); // if (svga_output) pclog("Write LFB %08X %02X ", addr, val);
if (!(svga->gdcreg[6] & 1)) if (!(svga->gdcreg[6] & 1))
svga->fullchange = 2; svga->fullchange = 2;
if (svga->gdcreg[0xb] & GRB_X8_ADDRESSING) if (svga->gdcreg[0xb] & GRB_ENHANCED_16BIT)
addr <<= 4;
else if (svga->gdcreg[0xb] & GRB_X8_ADDRESSING)
addr <<= 3; addr <<= 3;
else if (((svga->chain4 && svga->packed_chain4) || svga->fb_only) && (svga->writemode < 4)) else if (((svga->chain4 && svga->packed_chain4) || svga->fb_only) && (svga->writemode < 4))
{ {
@ -879,10 +882,9 @@ void gd5429_write_linear(uint32_t addr, uint8_t val, void *p)
switch (svga->writemode) switch (svga->writemode)
{ {
case 4: case 4:
if (svga->gdcreg[0xb] & 0x10) if (svga->gdcreg[0xb] & GRB_ENHANCED_16BIT)
{ {
// pclog("Writemode 4 : %X ", addr); // pclog("Writemode 4 : %X ", addr);
addr <<= 2;
svga->changedvram[addr >> 12] = changeframecount; svga->changedvram[addr >> 12] = changeframecount;
// pclog("%X %X %02x\n", addr, val, svga->gdcreg[0xb]); // pclog("%X %X %02x\n", addr, val, svga->gdcreg[0xb]);
if (val & svga->seqregs[2] & 0x80) if (val & svga->seqregs[2] & 0x80)
@ -951,10 +953,9 @@ void gd5429_write_linear(uint32_t addr, uint8_t val, void *p)
break; break;
case 5: case 5:
if (svga->gdcreg[0xb] & 0x10) if (svga->gdcreg[0xb] & GRB_ENHANCED_16BIT)
{ {
// pclog("Writemode 5 : %X ", addr); // pclog("Writemode 5 : %X ", addr);
addr <<= 2;
svga->changedvram[addr >> 12] = changeframecount; svga->changedvram[addr >> 12] = changeframecount;
// pclog("%X %X %02x\n", addr, val, svga->gdcreg[0xb]); // pclog("%X %X %02x\n", addr, val, svga->gdcreg[0xb]);
if (svga->seqregs[2] & 0x80) if (svga->seqregs[2] & 0x80)
@ -1194,12 +1195,16 @@ uint8_t gd5429_read_linear(uint32_t addr, void *p)
egareads++; egareads++;
if (svga->gdcreg[0xb] & GRB_X8_ADDRESSING) if (svga->gdcreg[0xb] & GRB_ENHANCED_16BIT)
latch_addr = (addr << 4) & svga->decode_mask;
else if (svga->gdcreg[0xb] & GRB_X8_ADDRESSING)
latch_addr = (addr << 3) & svga->decode_mask; latch_addr = (addr << 3) & svga->decode_mask;
else else
latch_addr = (addr << 2) & svga->decode_mask; latch_addr = (addr << 2) & svga->decode_mask;
if (svga->gdcreg[0xb] & GRB_X8_ADDRESSING) if (svga->gdcreg[0xb] & GRB_ENHANCED_16BIT)
addr <<= 4;
else if (svga->gdcreg[0xb] & GRB_X8_ADDRESSING)
addr <<= 3; addr <<= 3;
else if ((svga->chain4 && svga->packed_chain4) || svga->fb_only) else if ((svga->chain4 && svga->packed_chain4) || svga->fb_only)
{ {