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Added preliminary IRQ support for ATI Mach64, S3 Vision864/Trio32/Trio64, and S3 ViRGE.

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This commit is contained in:
SarahW 2017-06-01 21:51:02 +01:00
commit 617cfd7ef2
3 changed files with 133 additions and 14 deletions
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53
src/vid_s3.c
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@ -76,11 +76,14 @@ typedef struct s3_t
uint8_t id, id_ext, id_ext_pci;
uint8_t int_line;
int packed_mmio;
uint32_t linear_base, linear_size;
uint8_t pci_regs[256];
int card;
uint32_t vram_mask;
@ -131,8 +134,16 @@ typedef struct s3_t
int blitter_busy;
uint64_t blitter_time;
uint64_t status_time;
uint8_t subsys_cntl, subsys_stat;
} s3_t;
#define INT_VSY (1 << 0)
#define INT_GE_BSY (1 << 1)
#define INT_FIFO_OVR (1 << 2)
#define INT_FIFO_EMP (1 << 3)
#define INT_MASK 0xf
void s3_updatemapping();
void s3_accel_write(uint32_t addr, uint8_t val, void *p);
@ -154,6 +165,14 @@ static void s3_wait_fifo_idle(s3_t *s3)
}
}
static void s3_update_irqs(s3_t *s3)
{
if (s3->subsys_cntl & s3->subsys_stat & INT_MASK)
pci_set_irq(s3->card, PCI_INTA);
else
pci_clear_irq(s3->card, PCI_INTA);
}
void s3_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat, s3_t *s3);
#define WRITE8(addr, var, val) switch ((addr) & 3) \
@ -711,9 +730,19 @@ static void fifo_thread(void *param)
s3->blitter_time += end_time - start_time;
}
s3->blitter_busy = 0;
s3->subsys_stat |= INT_FIFO_EMP;
s3_update_irqs(s3);
}
}
static void s3_vblank_start(svga_t *svga)
{
s3_t *s3 = (s3_t *)svga->p;
s3->subsys_stat |= INT_VSY;
s3_update_irqs(s3);
}
static void s3_queue(s3_t *s3, uint32_t addr, uint32_t val, uint32_t type)
{
fifo_entry_t *fifo = &s3->fifo[s3->fifo_write_idx & FIFO_MASK];
@ -1105,9 +1134,12 @@ void s3_accel_out(uint16_t port, uint8_t val, void *p)
else switch (port)
{
case 0x42e8:
s3->subsys_stat &= ~val;
s3_update_irqs(s3);
break;
case 0x42e9:
s3->accel.subsys_cntl = val;
s3->subsys_cntl = val;
s3_update_irqs(s3);
break;
case 0x46e8:
s3->accel.setup_md = val;
@ -1140,9 +1172,9 @@ uint8_t s3_accel_in(uint16_t port, void *p)
switch (port)
{
case 0x42e8:
return 0;
return s3->subsys_stat;
case 0x42e9:
return 0;
return s3->subsys_cntl;
case 0x82e8:
s3_wait_fifo_idle(s3);
@ -2087,6 +2119,9 @@ uint8_t s3_pci_read(int func, int addr, void *p)
case 0x31: return 0x00;
case 0x32: return s3->pci_regs[0x32];
case 0x33: return s3->pci_regs[0x33];
case 0x3c: return s3->int_line;
case 0x3d: return PCI_INTA;
}
return 0;
}
@ -2099,7 +2134,7 @@ void s3_pci_write(int func, int addr, uint8_t val, void *p)
switch (addr)
{
case PCI_REG_COMMAND:
s3->pci_regs[PCI_REG_COMMAND] = val & 0x27;
s3->pci_regs[PCI_REG_COMMAND] = val & 0x23;
if (val & PCI_COMMAND_IO)
s3_io_set(s3);
else
@ -2130,6 +2165,10 @@ void s3_pci_write(int func, int addr, uint8_t val, void *p)
mem_mapping_disable(&s3->bios_rom.mapping);
}
return;
case 0x3c:
s3->int_line = val;
return;
}
}
@ -2181,10 +2220,12 @@ static void *s3_init(char *bios_fn, int chip)
else
svga->crtc[0x36] = 1 | (3 << 2) | (1 << 4) | (vram_sizes[vram] << 5);
svga->crtc[0x37] = 1 | (7 << 5);
svga->vblank_start = s3_vblank_start;
s3_io_set(s3);
pci_add(s3_pci_read, s3_pci_write, s3);
s3->card = pci_add(s3_pci_read, s3_pci_write, s3);
s3->pci_regs[0x04] = 7;
@ -2197,6 +2238,8 @@ static void *s3_init(char *bios_fn, int chip)
s3->wake_fifo_thread = thread_create_event();
s3->fifo_not_full_event = thread_create_event();
s3->fifo_thread = thread_create(fifo_thread, s3);
s3->int_line = 0;
return s3;
}