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Added preliminary IRQ support for ATI Mach64, S3 Vision864/Trio32/Trio64, and S3 ViRGE.

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This commit is contained in:
SarahW 2017-06-01 21:51:02 +01:00
commit 617cfd7ef2
3 changed files with 133 additions and 14 deletions
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53
src/vid_ati_mach64.c
View file

@ -71,6 +71,8 @@ typedef struct mach64_t
int type;
uint8_t pci_regs[256];
uint8_t int_line;
int card;
int bank_r[2];
int bank_w[2];
@ -197,6 +199,7 @@ typedef struct mach64_t
uint16_t pci_id;
uint32_t config_chip_id;
uint32_t block_decoded_io;
int use_block_decoded_io;
int pll_addr;
uint8_t pll_regs[16];
@ -552,6 +555,14 @@ void mach64_updatemapping(mach64_t *mach64)
}
}
static void mach64_update_irqs(mach64_t *mach64)
{
if ((mach64->crtc_int_cntl & 0xaa0024) & ((mach64->crtc_int_cntl << 1) & 0xaa0024))
pci_set_irq(mach64->card, PCI_INTA);
else
pci_clear_irq(mach64->card, PCI_INTA);
}
static inline void wake_fifo_thread(mach64_t *mach64)
{
thread_set_event(mach64->wake_fifo_thread); /*Wake up FIFO thread if moving from idle*/
@ -1671,6 +1682,7 @@ static void mach64_vblank_start(svga_t *svga)
int overlay_cmp_mix = (mach64->overlay_key_cntl >> 8) & 0xf;
mach64->crtc_int_cntl |= 4;
mach64_update_irqs(mach64);
svga->overlay.x = (mach64->overlay_y_x_start >> 16) & 0x7ff;
svga->overlay.y = mach64->overlay_y_x_start & 0x7ff;
@ -2230,6 +2242,7 @@ void mach64_ext_writeb(uint32_t addr, uint8_t val, void *p)
mach64->crtc_int_cntl = (mach64->crtc_int_cntl & 0x75) | (val & ~0x75);
if (val & 4)
mach64->crtc_int_cntl &= ~4;
mach64_update_irqs(mach64);
break;
case 0x1c: case 0x1d: case 0x1e: case 0x1f:
@ -3146,17 +3159,20 @@ static void mach64_io_set(mach64_t *mach64)
io_sethandler(0x03c0, 0x0020, mach64_in, NULL, NULL, mach64_out, NULL, NULL, mach64);
for (c = 0; c < 8; c++)
if (!mach64->use_block_decoded_io)
{
io_sethandler((c * 0x1000) + 0x2ec, 0x0004, mach64_ext_inb, mach64_ext_inw, mach64_ext_inl, mach64_ext_outb, mach64_ext_outw, mach64_ext_outl, mach64);
io_sethandler((c * 0x1000) + 0x6ec, 0x0004, mach64_ext_inb, mach64_ext_inw, mach64_ext_inl, mach64_ext_outb, mach64_ext_outw, mach64_ext_outl, mach64);
io_sethandler((c * 0x1000) + 0xaec, 0x0004, mach64_ext_inb, mach64_ext_inw, mach64_ext_inl, mach64_ext_outb, mach64_ext_outw, mach64_ext_outl, mach64);
io_sethandler((c * 0x1000) + 0xeec, 0x0004, mach64_ext_inb, mach64_ext_inw, mach64_ext_inl, mach64_ext_outb, mach64_ext_outw, mach64_ext_outl, mach64);
for (c = 0; c < 8; c++)
{
io_sethandler((c * 0x1000) + 0x2ec, 0x0004, mach64_ext_inb, mach64_ext_inw, mach64_ext_inl, mach64_ext_outb, mach64_ext_outw, mach64_ext_outl, mach64);
io_sethandler((c * 0x1000) + 0x6ec, 0x0004, mach64_ext_inb, mach64_ext_inw, mach64_ext_inl, mach64_ext_outb, mach64_ext_outw, mach64_ext_outl, mach64);
io_sethandler((c * 0x1000) + 0xaec, 0x0004, mach64_ext_inb, mach64_ext_inw, mach64_ext_inl, mach64_ext_outb, mach64_ext_outw, mach64_ext_outl, mach64);
io_sethandler((c * 0x1000) + 0xeec, 0x0004, mach64_ext_inb, mach64_ext_inw, mach64_ext_inl, mach64_ext_outb, mach64_ext_outw, mach64_ext_outl, mach64);
}
}
io_sethandler(0x01ce, 0x0002, mach64_in, NULL, NULL, mach64_out, NULL, NULL, mach64);
if (mach64->block_decoded_io && mach64->block_decoded_io < 0x10000)
if (mach64->use_block_decoded_io && mach64->block_decoded_io && mach64->block_decoded_io < 0x10000)
io_sethandler(mach64->block_decoded_io, 0x0400, mach64_block_inb, mach64_block_inw, mach64_block_inl, mach64_block_outb, mach64_block_outw, mach64_block_outl, mach64);
}
@ -3203,6 +3219,11 @@ uint8_t mach64_pci_read(int func, int addr, void *p)
case 0x31: return 0x00;
case 0x32: return mach64->pci_regs[0x32];
case 0x33: return mach64->pci_regs[0x33];
case 0x3c: return mach64->int_line;
case 0x3d: return PCI_INTA;
case 0x40: return mach64->use_block_decoded_io;
}
return 0;
}
@ -3280,6 +3301,21 @@ void mach64_pci_write(int func, int addr, uint8_t val, void *p)
mem_mapping_disable(&mach64->bios_rom.mapping);
}
return;
case 0x3c:
mach64->int_line = val;
break;
case 0x40:
if (mach64->type == MACH64_VT2)
{
if (mach64->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO)
mach64_io_remove(mach64);
mach64->use_block_decoded_io = val & 0x04;
if (mach64->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO)
mach64_io_set(mach64);
}
break;
}
}
@ -3308,7 +3344,7 @@ static void *mach64_common_init()
mach64_io_set(mach64);
pci_add(mach64_pci_read, mach64_pci_write, mach64);
mach64->card = pci_add(mach64_pci_read, mach64_pci_write, mach64);
mach64->pci_regs[PCI_REG_COMMAND] = 3;
mach64->pci_regs[0x30] = 0x00;
@ -3356,7 +3392,8 @@ static void *mach64vt2_init()
mach64->config_chip_id = 0x40005654;
mach64->dac_cntl = 1 << 16; /*Internal 24-bit DAC*/
mach64->config_stat0 = 4;
mach64->use_block_decoded_io = PCI ? 4 : 0;
ati_eeprom_load(&mach64->eeprom, "mach64vt.nvr", 1);
rom_init(&mach64->bios_rom, "roms/atimach64vt2pci.bin", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);

53
src/vid_s3.c
View file

@ -76,11 +76,14 @@ typedef struct s3_t
uint8_t id, id_ext, id_ext_pci;
uint8_t int_line;
int packed_mmio;
uint32_t linear_base, linear_size;
uint8_t pci_regs[256];
int card;
uint32_t vram_mask;
@ -131,8 +134,16 @@ typedef struct s3_t
int blitter_busy;
uint64_t blitter_time;
uint64_t status_time;
uint8_t subsys_cntl, subsys_stat;
} s3_t;
#define INT_VSY (1 << 0)
#define INT_GE_BSY (1 << 1)
#define INT_FIFO_OVR (1 << 2)
#define INT_FIFO_EMP (1 << 3)
#define INT_MASK 0xf
void s3_updatemapping();
void s3_accel_write(uint32_t addr, uint8_t val, void *p);
@ -154,6 +165,14 @@ static void s3_wait_fifo_idle(s3_t *s3)
}
}
static void s3_update_irqs(s3_t *s3)
{
if (s3->subsys_cntl & s3->subsys_stat & INT_MASK)
pci_set_irq(s3->card, PCI_INTA);
else
pci_clear_irq(s3->card, PCI_INTA);
}
void s3_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat, s3_t *s3);
#define WRITE8(addr, var, val) switch ((addr) & 3) \
@ -711,9 +730,19 @@ static void fifo_thread(void *param)
s3->blitter_time += end_time - start_time;
}
s3->blitter_busy = 0;
s3->subsys_stat |= INT_FIFO_EMP;
s3_update_irqs(s3);
}
}
static void s3_vblank_start(svga_t *svga)
{
s3_t *s3 = (s3_t *)svga->p;
s3->subsys_stat |= INT_VSY;
s3_update_irqs(s3);
}
static void s3_queue(s3_t *s3, uint32_t addr, uint32_t val, uint32_t type)
{
fifo_entry_t *fifo = &s3->fifo[s3->fifo_write_idx & FIFO_MASK];
@ -1105,9 +1134,12 @@ void s3_accel_out(uint16_t port, uint8_t val, void *p)
else switch (port)
{
case 0x42e8:
s3->subsys_stat &= ~val;
s3_update_irqs(s3);
break;
case 0x42e9:
s3->accel.subsys_cntl = val;
s3->subsys_cntl = val;
s3_update_irqs(s3);
break;
case 0x46e8:
s3->accel.setup_md = val;
@ -1140,9 +1172,9 @@ uint8_t s3_accel_in(uint16_t port, void *p)
switch (port)
{
case 0x42e8:
return 0;
return s3->subsys_stat;
case 0x42e9:
return 0;
return s3->subsys_cntl;
case 0x82e8:
s3_wait_fifo_idle(s3);
@ -2087,6 +2119,9 @@ uint8_t s3_pci_read(int func, int addr, void *p)
case 0x31: return 0x00;
case 0x32: return s3->pci_regs[0x32];
case 0x33: return s3->pci_regs[0x33];
case 0x3c: return s3->int_line;
case 0x3d: return PCI_INTA;
}
return 0;
}
@ -2099,7 +2134,7 @@ void s3_pci_write(int func, int addr, uint8_t val, void *p)
switch (addr)
{
case PCI_REG_COMMAND:
s3->pci_regs[PCI_REG_COMMAND] = val & 0x27;
s3->pci_regs[PCI_REG_COMMAND] = val & 0x23;
if (val & PCI_COMMAND_IO)
s3_io_set(s3);
else
@ -2130,6 +2165,10 @@ void s3_pci_write(int func, int addr, uint8_t val, void *p)
mem_mapping_disable(&s3->bios_rom.mapping);
}
return;
case 0x3c:
s3->int_line = val;
return;
}
}
@ -2181,10 +2220,12 @@ static void *s3_init(char *bios_fn, int chip)
else
svga->crtc[0x36] = 1 | (3 << 2) | (1 << 4) | (vram_sizes[vram] << 5);
svga->crtc[0x37] = 1 | (7 << 5);
svga->vblank_start = s3_vblank_start;
s3_io_set(s3);
pci_add(s3_pci_read, s3_pci_write, s3);
s3->card = pci_add(s3_pci_read, s3_pci_write, s3);
s3->pci_regs[0x04] = 7;
@ -2197,6 +2238,8 @@ static void *s3_init(char *bios_fn, int chip)
s3->wake_fifo_thread = thread_create_event();
s3->fifo_not_full_event = thread_create_event();
s3->fifo_thread = thread_create(fifo_thread, s3);
s3->int_line = 0;
return s3;
}

41
src/vid_s3_virge.c
View file

@ -127,6 +127,7 @@ typedef struct virge_t
uint32_t linear_base, linear_size;
uint8_t pci_regs[256];
int card;
int is_375;
@ -234,6 +235,8 @@ typedef struct virge_t
event_t *fifo_not_full_event;
int virge_busy;
uint8_t subsys_stat, subsys_cntl;
} virge_t;
static inline void wake_fifo_thread(virge_t *virge)
@ -298,6 +301,21 @@ enum
CMD_SET_COMMAND_NOP = (15 << 27)
};
#define INT_VSY (1 << 0)
#define INT_S3D_DONE (1 << 1)
#define INT_FIFO_OVF (1 << 2)
#define INT_FIFO_EMP (1 << 3)
#define INT_3DF_EMP (1 << 6)
#define INT_MASK 0xff
static void s3_virge_update_irqs(virge_t *virge)
{
if ((virge->svga.crtc[0x32] & 0x10) && (virge->subsys_stat & virge->subsys_cntl & INT_MASK))
pci_set_irq(virge->card, PCI_INTA);
else
pci_clear_irq(virge->card, PCI_INTA);
}
static void s3_virge_out(uint16_t addr, uint8_t val, void *p)
{
virge_t *virge = (virge_t *)p;
@ -353,6 +371,7 @@ static void s3_virge_out(uint16_t addr, uint8_t val, void *p)
case 0x32:
if ((svga->crtc[0x67] & 0xc) != 0xc)
svga->vrammask = (val & 0x40) ? 0x3ffff : ((virge->memory_size << 20) - 1);
s3_virge_update_irqs(virge);
break;
case 0x50:
@ -717,6 +736,14 @@ static void s3_virge_updatemapping(virge_t *virge)
}
static void s3_virge_vblank_start(svga_t *svga)
{
virge_t *virge = (virge_t *)svga->p;
virge->subsys_stat |= INT_VSY;
s3_virge_update_irqs(virge);
}
static void s3_virge_wait_fifo_idle(virge_t *virge)
{
while (!FIFO_EMPTY)
@ -851,6 +878,7 @@ static uint32_t s3_virge_mmio_read_l(uint32_t addr, void *p)
ret = (0x10 << 8);
else
ret = (0x10 << 8) | (1 << 13);
ret |= virge->subsys_stat;
if (!virge->virge_busy)
wake_fifo_thread(virge);
// pclog("Read status %04x %i\n", ret, virge->s3d_busy);
@ -1270,6 +1298,8 @@ static void fifo_thread(void *param)
virge_time += end_time - start_time;
}
virge->virge_busy = 0;
virge->subsys_stat |= INT_FIFO_EMP | INT_3DF_EMP;
s3_virge_update_irqs(virge);
}
}
@ -1480,6 +1510,12 @@ static void s3_virge_mmio_write_l(uint32_t addr, uint32_t val, void *p)
svga->fullchange = changeframecount;
break;
case 0x8504:
virge->subsys_stat &= ~(val & 0xff);
virge->subsys_cntl = (val >> 8);
s3_virge_update_irqs(virge);
break;
case 0xa000: case 0xa004: case 0xa008: case 0xa00c:
case 0xa010: case 0xa014: case 0xa018: case 0xa01c:
case 0xa020: case 0xa024: case 0xa028: case 0xa02c:
@ -3304,6 +3340,8 @@ static void render_thread(void *param)
thread_set_event(virge->not_full_event);
}
virge->s3d_busy = 0;
virge->subsys_stat |= INT_S3D_DONE;
s3_virge_update_irqs(virge);
}
}
@ -3857,6 +3895,7 @@ static void *s3_virge_375_init()
s3_virge_in, s3_virge_out,
s3_virge_hwcursor_draw,
s3_virge_overlay_draw);
virge->svga.vblank_start = s3_virge_vblank_start;
rom_init(&virge->bios_rom, "roms/86c375_1.bin", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
if (PCI)
@ -3925,7 +3964,7 @@ static void *s3_virge_375_init()
virge->is_375 = 1;
pci_add(s3_virge_pci_read, s3_virge_pci_write, virge);
virge->card = pci_add(s3_virge_pci_read, s3_virge_pci_write, virge);
virge->wake_render_thread = thread_create_event();
virge->wake_main_thread = thread_create_event();