Added emulation of Commodore SL386SX-25 (PC Player II).
As part of this, added emulation of the onboard AVGA2, and fixed a couple of bugs in the Cirrus Logic extended write modes. Currently chipset (VLSI SCAMP) is missing EMS emulation.
This commit is contained in:
SarahW
parent
f56f5e76e6
commit
5c8e1aecc2
12 changed files with 499 additions and 37 deletions
230
src/scamp.c
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230
src/scamp.c
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#include "ibm.h"
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#include "io.h"
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#include "mem.h"
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#include "scamp.h"
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static struct
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{
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int cfg_index;
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uint8_t cfg_regs[256];
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int cfg_enable;
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uint8_t port_92;
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} scamp;
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#define CFG_ID 0x00
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#define CFG_SLTPTR 0x02
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#define CFG_RAMMAP 0x03
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#define CFG_ABAXS 0x0e
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#define CFG_CAXS 0x0f
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#define CFG_DAXS 0x10
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#define CFG_FEAXS 0x11
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#define ID_VL82C311 0xd6
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#define RAMMAP_REMP386 (1 << 4)
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static void shadow_control(uint32_t addr, uint32_t size, int state)
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{
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// pclog("shadow_control: addr=%08x size=%04x state=%i\n", addr, size, state);
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switch (state)
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{
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case 0:
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mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
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break;
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case 1:
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mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
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break;
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case 2:
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mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
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break;
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case 3:
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mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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break;
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}
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flushmmucache_nopc();
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}
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void scamp_write(uint16_t addr, uint8_t val, void *p)
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{
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// pclog("scamp_write: addr=%04x val=%02x\n", addr, val);
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switch (addr)
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{
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case 0x92:
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if ((mem_a20_alt ^ val) & 2)
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{
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mem_a20_alt = val & 2;
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mem_a20_recalc();
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}
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if ((~scamp.port_92 & val) & 1)
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{
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softresetx86();
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cpu_set_edx();
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}
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scamp.port_92 = val;
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break;
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case 0xec:
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if (scamp.cfg_enable)
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scamp.cfg_index = val;
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break;
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case 0xed:
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if (scamp.cfg_enable)
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{
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if (scamp.cfg_index >= 0x02 && scamp.cfg_index <= 0x16)
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{
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scamp.cfg_regs[scamp.cfg_index] = val;
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// pclog("SCAMP CFG[%02x]=%02x\n", scamp.cfg_index, val);
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switch (scamp.cfg_index)
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{
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case CFG_SLTPTR:
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#if 0
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if (!val)
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{
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/*Disable all RAM*/
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mem_mapping_disable(&ram_low_mapping);
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mem_mapping_disable(&ram_high_mapping);
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}
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else if (val < 0x10)
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{
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mem_mapping_set_addr(&ram_low_mapping, 0, (val > 9) ? 0xa0000 : (val << 16));
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mem_mapping_disable(&ram_high_mapping);
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}
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else
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{
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mem_mapping_enable(&ram_low_mapping);
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mem_mapping_enable(&ram_high_mapping);
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}
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#endif
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break;
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case CFG_RAMMAP:
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mem_mapping_disable(&ram_remapped_mapping);
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if (scamp.cfg_regs[CFG_RAMMAP] & RAMMAP_REMP386)
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{
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/*Enabling remapping will disable all shadowing*/
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mem_remap_top_384k();
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shadow_control(0xa0000, 0x60000, 0);
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}
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else
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{
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shadow_control(0xa0000, 0x8000, scamp.cfg_regs[CFG_ABAXS] & 3);
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shadow_control(0xa8000, 0x8000, (scamp.cfg_regs[CFG_ABAXS] >> 2) & 3);
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shadow_control(0xb0000, 0x8000, (scamp.cfg_regs[CFG_ABAXS] >> 4) & 3);
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shadow_control(0xb8000, 0x8000, (scamp.cfg_regs[CFG_ABAXS] >> 6) & 3);
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shadow_control(0xc0000, 0x4000, scamp.cfg_regs[CFG_ABAXS] & 3);
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shadow_control(0xc4000, 0x4000, (scamp.cfg_regs[CFG_ABAXS] >> 2) & 3);
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shadow_control(0xc8000, 0x4000, (scamp.cfg_regs[CFG_ABAXS] >> 4) & 3);
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shadow_control(0xcc000, 0x4000, (scamp.cfg_regs[CFG_ABAXS] >> 6) & 3);
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shadow_control(0xd0000, 0x4000, scamp.cfg_regs[CFG_ABAXS] & 3);
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shadow_control(0xd4000, 0x4000, (scamp.cfg_regs[CFG_ABAXS] >> 2) & 3);
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shadow_control(0xd8000, 0x4000, (scamp.cfg_regs[CFG_ABAXS] >> 4) & 3);
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shadow_control(0xdc000, 0x4000, (scamp.cfg_regs[CFG_ABAXS] >> 6) & 3);
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shadow_control(0xe0000, 0x8000, scamp.cfg_regs[CFG_ABAXS] & 3);
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shadow_control(0xe8000, 0x8000, (scamp.cfg_regs[CFG_ABAXS] >> 2) & 3);
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shadow_control(0xf0000, 0x8000, (scamp.cfg_regs[CFG_ABAXS] >> 4) & 3);
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shadow_control(0xf8000, 0x8000, (scamp.cfg_regs[CFG_ABAXS] >> 6) & 3);
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}
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break;
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case CFG_ABAXS:
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if (!(scamp.cfg_regs[CFG_RAMMAP] & RAMMAP_REMP386))
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{
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shadow_control(0xa0000, 0x8000, val & 3);
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shadow_control(0xa8000, 0x8000, (val >> 2) & 3);
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shadow_control(0xb0000, 0x8000, (val >> 4) & 3);
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shadow_control(0xb8000, 0x8000, (val >> 6) & 3);
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}
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break;
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case CFG_CAXS:
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if (!(scamp.cfg_regs[CFG_RAMMAP] & RAMMAP_REMP386))
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{
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shadow_control(0xc0000, 0x4000, val & 3);
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shadow_control(0xc4000, 0x4000, (val >> 2) & 3);
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shadow_control(0xc8000, 0x4000, (val >> 4) & 3);
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shadow_control(0xcc000, 0x4000, (val >> 6) & 3);
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}
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break;
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case CFG_DAXS:
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if (!(scamp.cfg_regs[CFG_RAMMAP] & RAMMAP_REMP386))
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{
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shadow_control(0xd0000, 0x4000, val & 3);
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shadow_control(0xd4000, 0x4000, (val >> 2) & 3);
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shadow_control(0xd8000, 0x4000, (val >> 4) & 3);
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shadow_control(0xdc000, 0x4000, (val >> 6) & 3);
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}
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break;
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case CFG_FEAXS:
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if (!(scamp.cfg_regs[CFG_RAMMAP] & RAMMAP_REMP386))
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{
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shadow_control(0xe0000, 0x8000, val & 3);
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shadow_control(0xe8000, 0x8000, (val >> 2) & 3);
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shadow_control(0xf0000, 0x8000, (val >> 4) & 3);
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shadow_control(0xf8000, 0x8000, (val >> 6) & 3);
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}
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break;
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}
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}
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}
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break;
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case 0xee:
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if (scamp.cfg_enable && mem_a20_alt)
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{
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scamp.port_92 &= ~2;
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mem_a20_alt = 0;
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mem_a20_recalc();
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}
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break;
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}
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}
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uint8_t scamp_read(uint16_t addr, void *p)
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{
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uint8_t ret = 0xff;
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switch (addr)
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{
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case 0x92:
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ret = scamp.port_92;
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break;
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case 0xee:
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if (!mem_a20_alt)
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{
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scamp.port_92 |= 2;
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mem_a20_alt = 1;
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mem_a20_recalc();
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}
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break;
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case 0xef:
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softresetx86();
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cpu_set_edx();
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break;
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}
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// pclog("scamp_read: addr=%04x ret=%02x\n", addr, ret);
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return ret;
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}
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void scamp_init(void)
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{
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memset(&scamp, 0, sizeof(scamp));
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scamp.cfg_regs[CFG_ID] = ID_VL82C311;
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scamp.cfg_enable = 1;
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io_sethandler(0x0092, 0x0001, scamp_read, NULL, NULL, scamp_write, NULL, NULL, NULL);
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io_sethandler(0x00e8, 0x0001, scamp_read, NULL, NULL, scamp_write, NULL, NULL, NULL);
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io_sethandler(0x00ea, 0x0006, scamp_read, NULL, NULL, scamp_write, NULL, NULL, NULL);
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io_sethandler(0x00f4, 0x0002, scamp_read, NULL, NULL, scamp_write, NULL, NULL, NULL);
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io_sethandler(0x00f9, 0x0001, scamp_read, NULL, NULL, scamp_write, NULL, NULL, NULL);
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io_sethandler(0x00fb, 0x0001, scamp_read, NULL, NULL, scamp_write, NULL, NULL, NULL);
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}
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