From 5b2087f84dfa9e217f6ec514e0ce18fb742213ed Mon Sep 17 00:00:00 2001
From: SarahW <pcem@pcem-emulator.co.uk>
Date: Tue, 30 Jun 2020 21:20:53 +0100
Subject: [PATCH] Added Celeron emulation.

---
 src/cpu.c        | 15 ++++++++++++++-
 src/cpu.h        |  2 ++
 src/cpu_tables.c | 12 ++++++++++++
 3 files changed, 28 insertions(+), 1 deletion(-)

diff --git a/src/cpu.c b/src/cpu.c
index a08f2f1..3335a3e 100644
--- a/src/cpu.c
+++ b/src/cpu.c
@@ -1056,6 +1056,8 @@ void cpu_set()
                 break;
 
                 case CPU_PENTIUM_2:
+                case CPU_CELERON:
+                case CPU_CELERON_A:
                 x86_setopcodes(ops_386, ops_pentium2_0f, dynarec_ops_386, dynarec_ops_pentium2_0f);
                 x86_dynarec_opcodes_da_a16 = dynarec_ops_fpu_686_da_a16;
                 x86_dynarec_opcodes_da_a32 = dynarec_ops_fpu_686_da_a32;
@@ -1652,6 +1654,8 @@ void cpu_CPUID()
                 break;
                 
                 case CPU_PENTIUM_2:
+                case CPU_CELERON:
+                case CPU_CELERON_A:
                 if (!EAX)
                 {
                         EAX = 0x00000002;
@@ -1670,7 +1674,12 @@ void cpu_CPUID()
                         EAX = 0x03020101;
                         EBX = 0;
                         ECX = 0;
-                        EDX = 0x08040c43;
+                        if (models[model].cpu[cpu_manufacturer].cpus[cpu].cpu_type == CPU_PENTIUM_2)
+                                EDX = 0x08040c43; /*512kb L2 cache*/
+                        else if (models[model].cpu[cpu_manufacturer].cpus[cpu].cpu_type == CPU_CELERON)
+                                EDX = 0x08040c40; /*No L2 cache*/
+                        else
+                                EDX = 0x08040c41; /*128kb L2 cache*/
                 }
                 else
                         EAX = EBX = ECX = EDX = 0;
@@ -1752,6 +1761,8 @@ void cpu_RDMSR()
                 break;
                 case CPU_PENTIUMPRO:
                 case CPU_PENTIUM_2:
+                case CPU_CELERON:
+                case CPU_CELERON_A:
                 EAX = EDX = 0;
                 switch (ECX)
                 {
@@ -1859,6 +1870,8 @@ void cpu_WRMSR()
                 break;
                 case CPU_PENTIUMPRO:
                 case CPU_PENTIUM_2:
+                case CPU_CELERON:
+                case CPU_CELERON_A:
                 switch (ECX)
                 {
                         case 0x10:
diff --git a/src/cpu.h b/src/cpu.h
index 9a6ff03..dad9d2b 100644
--- a/src/cpu.h
+++ b/src/cpu.h
@@ -43,6 +43,8 @@ extern int fpu_type;
 #define CPU_K6_3P       27
 #define CPU_PENTIUMPRO  28
 #define CPU_PENTIUM_2   29
+#define CPU_CELERON     30
+#define CPU_CELERON_A   31
 
 #define MANU_INTEL 0
 #define MANU_AMD   1
diff --git a/src/cpu_tables.c b/src/cpu_tables.c
index 0c651f8..3ff519c 100644
--- a/src/cpu_tables.c
+++ b/src/cpu_tables.c
@@ -523,5 +523,17 @@ CPU cpus_Slot1_100MHz[] =
         {"Pentium II/350", CPU_PENTIUM_2, fpus_builtin, 20, 350000000, 3, 33333333, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 42},
         {"Pentium II/400", CPU_PENTIUM_2, fpus_builtin, 20, 400000000, 3, 33333333, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 48},
         {"Pentium II/450", CPU_PENTIUM_2, fpus_builtin, 20, 450000000, 3, 33333333, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 54},
+        {"Pentium II/266", CPU_PENTIUM_2, fpus_builtin, 20, 266666666, 3, 33333333, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 32},
+        {"Pentium II/300", CPU_PENTIUM_2, fpus_builtin, 20, 300000000, 3, 33333333, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 36},
+        {"Celeron 266",    CPU_CELERON,   fpus_builtin, 20, 266666666, 3, 33333333, 0x650, 0x650, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 32},
+        {"Celeron 300",    CPU_CELERON,   fpus_builtin, 20, 300000000, 3, 33333333, 0x650, 0x650, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 36},
+        {"Celeron-A 300",  CPU_CELERON_A, fpus_builtin, 20, 300000000, 3, 33333333, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 40},
+        {"Celeron 333",    CPU_CELERON_A, fpus_builtin, 20, 333333333, 3, 33333333, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 44},
+        {"Celeron 366",    CPU_CELERON_A, fpus_builtin, 20, 366666666, 3, 33333333, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 48},
+        {"Celeron 400",    CPU_CELERON_A, fpus_builtin, 20, 400000000, 3, 33333333, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 52},
+        {"Celeron 433",    CPU_CELERON_A, fpus_builtin, 20, 433333333, 3, 33333333, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 56},
+        {"Celeron 466",    CPU_CELERON_A, fpus_builtin, 20, 466666666, 3, 33333333, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 60},
+        {"Celeron 500",    CPU_CELERON_A, fpus_builtin, 20, 500000000, 3, 33333333, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 64},
+        {"Celeron 533",    CPU_CELERON_A, fpus_builtin, 20, 533333333, 3, 33333333, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 68},
         {"",             -1,        0, 0, 0}
 };